M41T80

Operation

Doc ID 9074 Rev 5

7/27

2

Operation

The M41T80 clock operates as a slave device on the serial bus. Access is obtained by

implementing a start condition followed by the correct slave address (D0h). The 20 bytes

contained in the device can then be accessed sequentially in the following order:

●

●

●

●

●

●

●

●

●

●

●

●

●

2.1

2-Wire bus characteristics

The bus is intended for communication between different IC’s. It consists of two lines: a bi-

directional data signal (SDA) and a clock signal (SCL). Both the SDA and SCL lines must be

connected to a positive supply voltage via a pull-up resistor.

The following protocol has been defined:

●

Data transfer may be initiated only when the bus is not busy.

●

During data transfer, the data line must remain stable whenever the clock line is high.

●

Changes in the data line, while the clock line is high, will be interpreted as control

signals.

Accordingly, the following bus conditions have been defined:

2.1.1

Bus not busy

Both data and clock lines remain high.

2.1.2

Start data transfer

A change in the state of the data line, from high to low, while the clock is high, defines the

START condition.

2.1.3

Stop data transfer

A change in the state of the data line, from low to high, while the clock is high, defines the

STOP condition.