WM8758CBGEFLSLASHV datasheet(23/90 Pages) WOLFSON

23 / 90 page

Production Data

WM8758B

PD, Rev 4.4, January 2012

Figure 10 ADC Power Up and Down Sequence (not to scale)

SYMBOL

MIN

TYPICAL

MAX

UNIT

tmidrail_on

300

tmidrail_off

tadcint

2/fs

/fs

ADC Group Delay

29/fs

/fs

Table 2 Typical POR Operation (typical values, not tested)

Notes:

The analogue input pin charge time, tmidrail_on, is determined by the VMID pin charge time. This

time is dependent upon the value of VMID decoupling capacitor and VMID pin input resistance

and AVDD power supply rise time.

The analogue input pin discharge time, tmidrail_off, is determined by the analogue input coupling

capacitor discharge time. The time, tmidrail_off, is measured using a 1μF capacitor on the analogue

input but will vary dependent upon the value of input coupling capacitor.

While the ADC is enabled there will be LSB data bit activity on the ADCDAT pin due to system

noise but no significant digital output will be present.

The VMIDSEL and BIASEN bits must be set to enable analogue input midrail voltage and for

normal ADC operation.

ADCDAT data output delay from power up - with power supplies starting from 0V - is determined

primarily by the VMID charge time. ADC initialisation and power management bits may be set

immediately after POR is released; VMID charge time will be significantly longer and will dictate

when the device is stabilised for analogue input.

ADCDAT data output delay at power up from device standby (power supplies already applied) is

determined by ADC initialisation time, 2/fs.

WM8758CBGEFL/V Datasheet(PDF) 23 Page - Wolfson Microelectronics plc