WM8321 datasheet(124/253 Pages) WOLFSON

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WM8321

Production Data

PD, February 2012, Rev 4.0

124

23.2.5 WATCHDOG INTERRUPTS

The primary WDOG_INT interrupt comprises a single secondary interrupt as described in Section 25.

The secondary interrupt bit is defined in Table 69.

The secondary interrupt can be masked. When the mask bit is set, the corresponding interrupt event

is masked and does not trigger a WDOG_INT interrupt. The secondary interrupt bit in R16401

(4011h) is valid regardless of whether the mask bit is set. The secondary interrupt is masked by

default.

ADDRESS

BIT

LABEL

DESCRIPTION

R16401

(4011h)

Interrupt Status

WDOG_TO_EINT

Watchdog timeout interrupt.

(Rising Edge triggered)

Note: Cleared when a ‘1’ is written.

R16409

(4019h)

Interrupt Status

1 Mask

IM_WDOG_TO_EINT

Interrupt mask.

0 = Do not mask interrupt.

1 = Mask interrupt.

Default value is 1 (masked)

Table 69 Watchdog Timer Interrupts

23.2.6 AUXADC INTERRUPTS

The primary AUXADC_INT interrupt comprises five secondary interrupts as described in Section 18.5.

The secondary interrupt bits are defined in Table 70.

Each of the secondary interrupts can be masked. When a mask bit is set, the corresponding interrupt

event is masked and does not trigger a AUXADC_INT interrupt. The secondary interrupt bits in

R16401 (4011h) are valid regardless of whether the mask bit is set. The secondary interrupts are all

masked by default.

ADDRESS

BIT

LABEL

DESCRIPTION

R16401

(4011h)

Interrupt Status

AUXADC_DATA_EINT

AUXADC Data Ready interrupt

(Rising Edge triggered)

Note: Cleared when a ‘1’ is written.

7:4

AUXADC_DCOMPn_EINT

AUXADC Digital Comparator n interrupt

(Trigger is controlled by DCMPn_GT)

Note: Cleared when a ‘1’ is written.

R16409

(4019h)

Interrupt Status

1 Mask

IM_AUXADC_DATA_EINT

Interrupt mask.

0 = Do not mask interrupt.

1 = Mask interrupt.

Default value is 1 (masked)

7:4

IM_AUXADC_DCOMPn_EI

Interrupt mask.

0 = Do not mask interrupt.

1 = Mask interrupt.

Default value is 1 (masked)

Note: n

is a number between 1 and 4 that identifies the individual Comparator.

Table 70 AUXADC Interrupts

23.2.7 POWER PATH MANAGEMENT INTERRUPTS

The primary PPM_INT interrupt comprises a single secondary interrupt as described in Section 17.2.

The secondary interrupt bit is defined in Table 71.

The secondary interrupt can be masked. When the mask bit is set, the corresponding interrupt event

is masked and does not trigger a PPM_INT interrupt. The secondary interrupt bit in R16401 (4011h)

are valid regardless of whether the mask bit is set. The secondary interrupt is masked by default.

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