WM8321 datasheet(126/253 Pages) WOLFSON

126 / 253 page

WM8321

Production Data

PD, February 2012, Rev 4.0

126

23.2.9 OTP MEMORY INTERRUPTS

The primary OTP_INT interrupt comprises two secondary interrupts as described in Section 14.5. The

secondary interrupt bits are defined in Table 73.

Each of the secondary interrupts can be masked. When a mask bit is set, the corresponding interrupt

event is masked and does not trigger a OTP_INT interrupt. The secondary interrupt bits in R16402

(4012h) are valid regardless of whether the mask bit is set. The secondary interrupts are all masked

by default.

ADDRESS

BIT

LABEL

DESCRIPTION

R16402

(4012h)

Interrupt Status

OTP_CMD_END_EINT

OTP / ICE Command End interrupt

(Rising Edge triggered)

Note: Cleared when a ‘1’ is written.

OTP_ERR_EINT

OTP / ICE Command Fail interrupt

(Rising Edge triggered)

Note: Cleared when a ‘1’ is written.

R16410

(401Ah)

Interrupt Status

2 Mask

IM_OTP_CMD_END_EINT

Interrupt mask.

0 = Do not mask interrupt.

1 = Mask interrupt.

Default value is 1 (masked)

IM_OTP_ERR_EINT

Interrupt mask.

0 = Do not mask interrupt.

1 = Mask interrupt.

Default value is 1 (masked)

Table 73 OTP Memory Interrupts

23.2.10 HIGH CURRENT INTERRUPTS

The primary HC_INT interrupt comprises two secondary interrupts as described in Section 15.12. The

secondary interrupt bits are defined in Table 74.

Each of the secondary interrupts can be masked. When a mask bit is set, the corresponding interrupt

event is masked and does not trigger a HC_INT interrupt. The secondary interrupt bits in R16404

(4014h) are valid regardless of whether the mask bit is set. The secondary interrupts are all masked

by default.

ADDRESS

BIT

LABEL

DESCRIPTION

R16404

(4014h)

Interrupt Status

HC_DC2_EINT

DC-DC2 High Current interrupt

(Rising Edge triggered)

Note: Cleared when a ‘1’ is written.

HC_DC1_EINT

DC-DC1 High Current interrupt

(Rising Edge triggered)

Note: Cleared when a ‘1’ is written.

R16412

(401Ch)

Interrupt Status

4 Mask

IM_HC_DC2_EINT

Interrupt mask.

0 = Do not mask interrupt.

1 = Mask interrupt.

Default value is 1 (masked)

IM_HC_DC1_EINT

Interrupt mask.

0 = Do not mask interrupt.

1 = Mask interrupt.

Default value is 1 (masked)

Table 74 Overcurrent Interrupts

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