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RT7259 Datasheet(PDF) 13 Page - Richtek Technology Corporation |
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RT7259 Datasheet(HTML) 13 Page - Richtek Technology Corporation |
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13 / 15 page ![]() 13 DS7259-00 January 2012 www.richtek.com RT7259 © Copyright 2012 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation. Table 4. Suggested Capacitors for CIN and COUT Location Component Supplier Part No. Capacitance ( μF) Case Size CIN MURATA GRM31CR61E106K 10 1206 CIN TDK C3225X5R1E106K 10 1206 CIN TAIYO YUDEN TMK316BJ106ML 10 1206 COUT MURATA GRM31CR60J476M 47 1206 COUT TDK C3225X5R0J476M 47 1210 COUT MURATA GRM32ER71C226M 22 1210 COUT TDK C3225X5R1C22M 22 1210 Checking Transient Response The regulator loop response can be checked by looking at the load transient response. Switching regulators take several cycles to respond to a step load change. When a step load occurs, VOUT immediately shifts by an amount equal to ΔILOAD x ESR also begins to charge or discharge COUT generating a feedback error signal for the regulator to return VOUT to its steady-state value. During this recovery time, VOUT can be monitored for overshoot or ringing that would indicate a stability problem. Thermal Considerations For continuous operation, do not exceed absolute maximum junction temperature. The maximum power dissipation depends on the thermal resistance of the IC package, PCB layout, rate of surrounding airflow, and difference between junction and ambient temperature. The maximum power dissipation can be calculated by the following formula : PD(MAX) = (TJ(MAX) − TA) / θJA where TJ(MAX) is the maximum junction temperature, TA is the ambient temperature, and θJAis the junction to ambient thermal resistance. For recommended operating condition specifications of the RT7259, the maximum junction temperature is 125 °C. The junction to ambient thermal resistance, θJA, is layout dependent. For WDFN-14L 4x3 package, the thermal resistance, θJA, is 60°C/W on a standard JEDEC 51-7 four-layer thermal test board. The output ripple will be the highest at the maximum input voltage since ΔIL increases with input voltage. Multiple capacitors placed in parallel may be needed to meet the ESR and RMS current handling requirement. Higher values, lower cost ceramic capacitors are now becoming available in smaller case sizes. Their high ripple current, high voltage rating and low ESR make them ideal for switching regulator applications. When a ceramic capacitor is used at the input and the power is supplied by a wall adapter through long wires, a load step at the output can induce ringing at the input, VIN. This ringing can couple to the output and be mistaken. A sudden inrush of current through the long wires can potentially cause a voltage spike at VIN large enough to damage the part. For the input capacitor, two 10 μF low ESR ceramic capacitors are recommended. For the recommended capacitor, please refer to Table 4 for more details. The selection of COUT is determined by the required ESR to minimize voltage ripple. Moreover, the amount of bulk capacitance is also a key for COUT selection to ensure that the control loop is stable. Loop stability can be checked by viewing the load transient response as described in a later section. The output ripple, ΔVOUT , is determined by : OUT L OUT 1 VI ESR 8fC ⎡⎤ Δ≤ Δ + ⎢⎥ ⎣⎦ |
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