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W49V002FAQ Datasheet(PDF) 19 Page - Winbond |
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W49V002FAQ Datasheet(HTML) 19 Page - Winbond |
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19 / 32 page  W49V002FA Publication Release Date: February 19, 2002 - 19 - Revision A2 Timing Waveforms for Programmer Interface Mode, continued Toggle Bit Timing Diagram A[10:0] DQ6 TOET TEC TBP or #OE #WE #C R/ Boot Block Lockout Enable Timing Diagram SB2 SB1 SB0 DQ[7:0] SB3 SB4 SB5 TWC TWP TWPH AA 55 80 AA 55 40 Note: The internal address A[17:0] are converted from external Column/Row address. Column/Row Address are mapped to the Low/High order internal address. i.e. Column Address A[10:0] are mapped to the internal A[10:0], Row Address A[6:0] are mapped to the internal A[17:11]. (Internal A[17:0]) Six-byte code for 3.3V-only software chip erase 5555 2AAA 5555 5555 2AAA 5555 A[10:0] #OE #WE #C R/ |
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