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41594B Datasheet(PDF) 230 Page - Microchip Technology |
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41594B Datasheet(HTML) 230 Page - Microchip Technology |
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230 / 372 page  Receiving Address Receive Data Receive Data A7 A6 A5 A4 A3 A2 A1 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 SDA SCL SSP1IF BF ACKDT CKP S P ACK S 12 34 56 7 8 9 12 3 45 6 7 8 9 12 34 5 6 7 8 9 ACK ACK Cleared by software ACKTIM is cleared by hardware SSP1BUF can be Set by software, read any time before next byte is loaded release SCL on 9th rising edge of SCL Received address is loaded into SSP1BUF Slave software clears ACKDT to ACK R/W = 0 Master releases SDA to slave for ACK sequence the received byte When AHEN = 1; on the 8th falling edge of SCL of an address byte, CKP is cleared ACKTIM is set by hardware on 8th falling edge of SCL When DHEN = 1; on the 8th falling edge of SCL of a received data byte, CKP is cleared Received data is available on SSP1BUF Slave sends not ACK CKP is not cleared if not ACK P Master sends Stop condition No interrupt after if not ACK from Slave ACKTIM |
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