41594B datasheet(242/372 Pages) MICROCHIP

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PIC12LF1840T48A

DS41594B-page 242

Preliminary

 2011-2012 Microchip Technology Inc.

25.6.2 CLOCK ARBITRATION

Clock arbitration occurs when the master, during any

receive, transmit or Repeated Start/Stop condition,

releases the SCL pin (SCL allowed to float high). When

the SCL pin is allowed to float high, the Baud Rate Gen-

erator (BRG) is suspended from counting until the SCL

pin is actually sampled high. When the SCL pin is sam-

pled high, the Baud Rate Generator is reloaded with

the contents of SSP1ADD<7:0> and begins counting.

This ensures that the SCL high time will always be at

least one BRG rollover count in the event that the clock

is held low by an external device (Figure 25-25).

FIGURE 25-25:

BAUD RATE GENERATOR TIMING WITH CLOCK ARBITRATION

25.6.3 WCOL STATUS FLAG

If the user writes the SSP1BUF when a Start, Restart,

Stop, Receive or Transmit sequence is in progress, the

WCOL bit is set and the contents of the buffer are

unchanged (the write does not occur). Any time the

WCOL bit is set it indicates that an action on SSP1BUF

was attempted while the module was not Idle.

25.6.4

I2C MASTER MODE START

CONDITION TIMING

To initiate a Start condition, the user sets the Start

Enable bit, SEN bit of the SSP1CON2 register. If the

SDA and SCL pins are sampled high, the Baud Rate

Generator

reloaded

with

the

contents

SSP1ADD<7:0> and starts its count. If SCL and SDA

are both sampled high when the Baud Rate Generator

times out (Tpwrt), the SDA pin is driven low. The

action of the SDA being driven low while SCL is high is

the Start condition and causes the S bit of the

SSP1STAT1 register to be set. Following this, the

Baud Rate Generator is reloaded with the contents of

SSP1ADD<7:0> and resumes its count. When the

Baud Rate Generator times out (Tpwrt), the SEN bit of

the SSP1CON2 register will be automatically cleared

by hardware; the Baud Rate Generator is suspended,

leaving the SDA line held low and the Start condition is

complete.

SDA

SCL

SCL deasserted but slave holds

DX ‚

– 1

BRG

SCL is sampled high, reload takes

place and BRG starts its count

03h

02h

01h

00h (hold off)

03h

02h

Reload

BRG

Value

SCL low (clock arbitration)

SCL allowed to transition high

BRG decrements on

Q2 and Q4 cycles

Note:

Because queueing of events is not

allowed, writing to the lower 5 bits of

SSP1CON2 is disabled until the Start

condition is complete.

Note 1: If at the beginning of the Start condition,

the SDA and SCL pins are already sam-

pled low, or if during the Start condition,

the SCL line is sampled low before the

SDA line is driven low, a bus collision

occurs, the Bus Collision Interrupt Flag,

BCL1IF, is set, the Start condition is

aborted and the I2C module is reset into

its Idle state.

2: The Philips I2C Specification states that a

bus collision cannot occur on a Start.

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