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41594B Datasheet(PDF) 287 Page - Microchip Technology |
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41594B Datasheet(HTML) 287 Page - Microchip Technology |
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287 / 372 page ![]() 2011-2012 Microchip Technology Inc. Preliminary DS41594B-page 287 PIC12LF1840T48A FIGURE 26-12: SYNCHRONOUS RECEPTION (MASTER MODE, SREN) TABLE 26-8: SUMMARY OF REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER RECEPTION Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on Page BAUDCON ABDOVF RCIDL — SCKP BRG16 — WUE ABDEN 274 INTCON GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 83 PIE1 TMR1GIE ADIE RCIE TXIE SSP1IE CCP1IE TMR2IE TMR1IE 84 PIR1 TMR1GIF ADIF RCIF TXIF SSP1IF CCP1IF TMR2IF TMR1IF 86 RCREG EUSART Receive Data Register 268* RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 273 SPBRGL BRG<7:0> 275* SPBRGH BRG<15:8> 275* TXSTA CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 272 Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used for synchronous master reception. * Page provides register information. CREN bit RX/DT Write to bit SREN SREN bit RCIF bit (Interrupt) Read RCREG ‘0’ bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 ‘0’ Note: Timing diagram demonstrates Sync Master mode with bit SREN = 1 and bit BRGH = 0. TX/CK pin TX/CK pin pin (SCKP = 0) (SCKP = 1) |
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