AD5533 datasheet(4/16 Pages) AD

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AD5533

–4–

REV. 0

TIMING CHARACTERISTICS

PARALLEL INTERFACE

Limit at TMIN, TMAX

Parameter

1, 2

(A Version)

Unit

Conditions/Comments

ns min

CS to WR Setup Time

ns min

CS to WR Hold Time

ns min

CS Pulsewidth Low

ns min

WR Pulsewidth Low

ns min

A4–A0, CAL, OFFS_SEL to

WR Setup Time

ns min

A4–A0, CAL, OFFS_SEL to

WR Hold Time

NOTES

1See Interface Timing Diagram.

2Guaranteed by design and characterization, not production tested.

Speciﬁcations subject to change without notice.

SERIAL INTERFACE

Limit at TMIN, TMAX

Parameter

1, 2

(A Version)

Unit

Conditions/Comments

fCLKIN

MHz max

SCLK Frequency

ns min

SCLK High Pulsewidth

ns min

SCLK Low Pulsewidth

ns min

SYNC Falling Edge to SCLK Falling Edge Setup Time

ns min

SYNC Low Time

ns min

DIN Setup Time

ns min

DIN Hold Time

ns min

SYNC Falling Edge to SCLK Rising Edge Setup Time

ns max

SCLK Rising Edge to DOUT Valid

ns max

SCLK Falling Edge to DOUT High Impedance

t10

400

ns min

10th SCLK Falling Edge to

SYNC Falling Edge for Readback

NOTES

1See Serial Interface Timing Diagrams.

2Guaranteed by design and characterization, not production tested.

3These numbers are measured with the load circuit of Figure 2.

Speciﬁcations subject to change without notice.

PARALLEL INTERFACE TIMING DIAGRAM

A4–A0, CAL,

OFFS SEL

Figure 1. Parallel Write (SHA Mode Only)

IOL

200 A

IOH

200 A

50pF

OUTPUT

1.6V

Figure 2. Load Circuit for DOUT Timing Speciﬁcations

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