AD5544ARS datasheet(8/16 Pages) AD

8 / 16 page

REV. 0

AD5544/AD5554

–8–

AD5544/AD5554 PIN FUNCTION DESCRIPTIONS

Pin # Name

Function

1AGNDA

DAC A Analog Ground.

2IOUTA

DAC A Current Output.

3VREFA

DAC A Reference Voltage Input Terminal. Establishes DAC A full-scale output voltage. Pin can be tied to VDD pin.

4RFBA

Establish Voltage Output for DAC A by Connecting to External Ampliﬁer Output.

MSB

MSB Bit Set Pin During a Reset Pulse (

RS) or at System Power ON if Tied to Ground or V

DD.

Reset Pin, Active Low Input. Input registers and DAC registers are set to all zeros or half-scale code (8000H for

AD5544 and 2000H for AD5554) determined by the voltage on the MSB pin. Register Data = 0000H when MSB

= 0. Register Data = 8000H for AD5544 and 2000H for AD5554 when MSB = 1.

7VDD

Positive Power Supply Input. Speciﬁed range of operation 5 V

± 10%.

Chip Select, Active Low Input. Disables shift register loading when high. Transfers serial register data to the Input

CS/LDAC returns High. Does not effect LDAC operation.

CLK

Clock Input, Positive Edge Clocks Data into Shift Register.

SDI

Serial Data Input, Input Data Loads Directly into the Shift Register.

RFBB

Establish Voltage Output for DAC B by Connecting to External Ampliﬁer Output.

VREFB

DAC B Reference Voltage Input Terminal. Establishes DAC B full-scale output voltage. Pin can be tied to VDD pin.

IOUTB

DAC B Current Output.

AGNDB

DAC B Analog Ground.

AGNDC

DAC C Analog Ground.

IOUTC

DAC C Current Output.

VREFC

DAC C Reference Voltage Input Terminal. Establishes DAC C full-scale output voltage. Pin can be tied to VDD pin.

RFBC

Establish voltage output for DAC C by connecting to external ampliﬁer output.

No Connect. Leave pin unconnected.

SDO

Serial Data Output, input data loads directly into the shift register. Data appears at SDO, 19 clock pulses for

AD5544 and 17 clock pulses for AD5554 after input at the SDI pin.

LDAC

Load DAC Register Strobe, Level Sensitive Active Low. Transfers all Input Register data to DAC registers. Asyn-

chronous active low input. See Control Logic Truth Table for operation.

AGNDF

High Current Analog Force Ground.

VSS

Negative Bias Power Supply Input. Speciﬁed range of operation –0.3 V to –5.5 V.

DGND

Digital Ground Pin.

RFBD

Establish Voltage Output for DAC D by Connecting to External Ampliﬁer Output.

VREFD

DAC D Reference Voltage Input Terminal. Establishes DAC D full-scale output voltage. Pin can be tied to VDD pin.

IOUTD

DAC D Current Output.

AGNDD

DAC D Analog Ground.

AD5544/AD5554 PIN CONFIGURATION

TOP VIEW

(Not to Scale)

AD5544/

AD5554

AGNDAAGNDD

IOUTAIOUTD

VREFAVREFD

RFBARFBD

MSB

DGND

VSS

VDD

AGNDF

LDAC

CLK

SDO

SDI

RFBBRFBC

VREFBVREFC

IOUTBIOUTC

AGNDBAGNDC

NC = NO CONNECT

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