AD5317 datasheet(12/20 Pages) AD

12 / 20 page

REV. 0

AD5330/AD5331/AD5340/AD5341

–12–

GAIN ERROR

VDD – Volts

0.2

–0.6

–0.4

TA = 25 C

VREF = 2V

–0.5

–0.3

–0.2

–0.1

0.1

OFFSET ERROR

Figure 14. Offset Error and Gain

Error vs. VDD

VDD – Volts

300

200

3.0

5.0

3.5

4.0

4.5

100

TA = 25 C

2.5

5.5

Figure 17. Supply Current vs. Supply

Voltage

CH1 1V, CH2 5V, TIME BASE = 5 s/DIV

CH2

CH1

CLK

VOUT

VDD = 5V

TA = 25 C

Figure 20. Half-Scale Settling (1/4 to

3/4 Scale Code Change)

5V SOURCE

SINK/SOURCE CURRENT – mA

3V SOURCE

3V SINK

5V SINK

Figure 15. VOUT Source and Sink

Current Capability

VDD – Volts

0.2

3.0

5.0

3.5

4.0

4.5

0.1

TA = 25 C

2.5

5.5

0.3

0.4

0.5

Figure 18. Power-Down Current vs.

Supply Voltage

VDD

CH1

CH2

VOUTA

TA = 25 C

VDD = 5V

VREF = 2V

CH1 2V, CH2 200mV, TIME BASE = 200 s/DIV

Figure 21. Power-On Reset to 0 V

DAC CODE

300

250

ZERO-SCALE

FULL-SCALE

200

150

100

VDD = 3.6V

VDD = 5.5V

TA = 25 C

VREF = 2V

Figure 16. Supply Current vs. DAC

Code

VLOGIC – Volts

400

200

600

800

1000

1200

1400

1600

1800

TA = 25 C

VDD = 3V

VDD = 5V

Figure 19. Supply Current vs. Logic

Input Voltage

CH1 500mV, CH2 5V, TIME BASE = 1 s/DIV

CH1

CH2

TA = 25 C

VDD = 5V

VREF = 2V

VOUTA

Figure 22. Exiting Power-Down to

Midscale

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