AD6140ARS datasheet(2/8 Pages) AD

2 / 8 page

REV. 0

–2–

AD6140–SPECIFICATIONS (T

A = +25 C, VCC = 2.7 V, VOLTAGE_REFERENCE_IN = 1 V, unless otherwise noted)

Specification

Conditions

Min

Typ

Max

Units

OVERALL

VOLTAGE_REFERENCE_IN = 1 V

± 5% dc,

IF = 49.6 MHz

LO = 49.792 MHz or 49.408 MHz, 200 mV p-p

Differential Input

Clock = 6.144 MHz, 800 mV p-p Differential ECL

Input, Clock Asymmetry = 50

± 2.5%

Input Third Order Intercept Point

At Max Gain

–27

–19

dBm

Noise Figure

At Max Gain, External Termination

10.5

Input Resistance

At IF_INPUT (Pin 19)

2.5

Ω

Input Capacitance

At IF_INPUT (Pin 19)

Dynamic Range

6.25 kHz Bandwidth Centered at 192 kHz

Maximum Gain

29.5

Minimum Gain

AGC DETECTOR

AGC Threshold

–24

dBm

Capacitor Charging Current

AGC_TC_SELECT Input = Logic LOW (FAST AGC)

2.8

µA

AGC_TC_SELECT Input = Logic HIGH (SLOW AGC)

ECL-TO-CMOS LEVEL

VDD (to VDD – 0.8 V) Differential Levels

TRANSLATOR

Clock Output Drive

5 pF Load

2.6

V p-p

Clock Asymmetry

5 pF Load

±2.5

LNA BIAS AMPLIFIER VOLTAGE

LNA_FORCE

2.9 V LNA_SENSE, Minimum Gain

1.7

LNA_SENSE Input Voltage Range

VDD

VDD – 0.3

POWER-DOWN INTERFACE

Logic Threshold

0.7

Turn-On Response Time

To Valid Data Output

100

µs

Turn-Off Response Time

To Typical Power-Down Supply Current

100

µs

POWER SUPPLY

Supply Voltage

2.5

2.9

Supply Current

Power-Down Input: Logic LOW = ON, IF_Input = 0 V

4.8

5.75

Power-Down Current

Power-Down Input: Logic HIGH = OFF

µA

Operating Temperature Range

–40

+85

°C

Specifications subject to change without notice.

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