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AD7466 Datasheet(PDF) 2 Page - Analog Devices |
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AD7466 Datasheet(HTML) 2 Page - Analog Devices |
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2 / 15 page  –2– REV. PrC AD7466–SPECIFICATIONS1 Parameter B Version 1, 2 Unit Test Conditions/Comments DYNAMIC PERFORMANCE fIN = 30 kHz Sine Wave Signal-to-Noise + Distortion (SINAD) 2 7 0 dB min Signal-to-Noise Ratio (SNR) 2 7 1 dB min Total Harmonic Distortion (THD) 2 – 7 8 dB typ Peak Harmonic or Spurious Noise (SFDR) 2 – 8 0 dB typ Intermodulation Distortion (IMD)2 fa = 29.1 kHz, fb = 29.9 kHz Second Order Terms – 7 8 dB typ Third Order Terms – 7 8 dB typ Aperture Delay 1 0 ns typ Aperture Jitter 3 0 ps typ Full Power Bandwidth T B D MHz typ @ 3 dB Full Power Bandwidth T B D MHz typ @ 0.1 dB DC ACCURACY Resolution 1 2 Bits Integral Nonlinearity 2 ±1.5 LSB max ±0.6 LSB typ Differential Nonlinearity2 –0.9/+1.5 LSB max Guaranteed No Missed Codes to 12 Bits ±0.75 LSB typ Offset Error 3 ±1.5 LSB max Gain Error3 ±1.5 LSB max ANALOG INPUT Input Voltage Ranges 0 to VDD V DC Leakage Current ±1 µA max Input Capacitance 3 0 pF typ LOGIC INPUTS Input High Voltage, VINH 0.7(VDD) V min VDD = 1.8 V to 3.6 V Input Low Voltage, VINL 0.4 V max Input Current, IIN, SCLK Pin ±1 µA max Typically 10 nA, VIN = 0 V or VDD Input Current, IIN, CS Pin ±1 µA typ Input Capacitance, CIN 2,3 1 0 pF max LOGIC OUTPUTS Output High Voltage, VOH VDD – 0.2 V min ISOURCE = 200 µA; VDD = 1.8 V to 3.6 V Output Low Voltage, VOL 0.2 V max ISINK = 200 µA Floating-State Leakage Current ±10 µA max Floating-State Output Capacitance 2,3 1 0 pF max Output Coding Straight (Natural) Binary CONVERSION RATE Conversion Time 6.66 µs max Sixteen SCLK Cycles Track/Hold Acquisition Time T B D ns max Full-Scale Step Input T B D ns max Sine Wave Input Throughput Rate 100 kSPS max See Serial Interface Section POWER REQUIREMENTS VDD 1.8/3.6 V min/max IDD Digital I/Ps = 0 V or VDD Normal Mode (Operational) 350 µA max VDD = 3 V. SCLK On or Off 200 µA max VDD = 1.8 V. SCLK On or Off Power-Down 0.5 µA max SCLK Off 8 0 µA max SCLK On Power Dissipation4 Normal Mode (Operational) T B D mW max VDD = 3 V. fSAMPLE = TBD mW max VDD = 1.8 V. fSAMPLE = TBD Power-Down 1.5 µW max VDD = 3 V. SCLK Off 0.9 µW max VDD = 1.8 V. SCLK Off NOTES 1Temperaturerangesasfollows:BVersions:–40°Cto+85°C. 2SeeTerminology. 3Sampletestedat25°Ctoensurecompliance. 4SeePowerVersusThroughputRatesection. Specificationssubjecttochangewithoutnotice. (VDD = 1.8 V to 3.6 V, fSCLK = 2.4 MHz, fSAMPLE = 100 kSPS unless otherwise noted; TA = TMIN to TMAX, unless otherwise noted.) pecifications |
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