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PCAL9539APW Datasheet(PDF) 34 Page - NXP Semiconductors |
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PCAL9539APW Datasheet(HTML) 34 Page - NXP Semiconductors |
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34 / 48 page ![]() PCAL9539A All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved. Product data sheet Rev. 1 — 3 October 2012 34 of 48 NXP Semiconductors PCAL9539A 16-bit I2C-bus and SMBus low power I/O port with interrupt and reset 14. Parameter measurement information Table 35. Switching characteristics Over recommended operating free air temperature range; CL 100 pF; unless otherwise specified. See Figure 29. Symbol Parameter Conditions Standard-mode I2C-bus Fast-mode I2C-bus Unit Min Max Min Max tv(INT) valid time on pin INT from P port to INT -1- 1 s trst(INT) reset time on pin INT from SCL to INT -1- 1 s tv(Q) data output valid time from SCL to P port - 400 - 400 ns tsu(D) data input set-up time from P port to SCL 0 - 0 - ns th(D) data input hold time from P port to SCL 300 - 300 - ns a. SDA load configuration b. Transaction format c. Voltage waveforms CL includes probe and jig capacitance. All inputs are supplied by generators having the following characteristics: PRR 10 MHz; Z o =50 ; tr/tf 30 ns. All parameters and waveforms are not applicable to all devices. Byte 1 = I2C-bus address; Byte 2, byte 3 = P port data. (1) See Figure 9. Fig 29. I2C-bus interface load circuit and voltage waveforms 002aag803 DUT CL = 50 pF RL = 1 kΩ SDA VDD STOP condition (P) Data Bit 0 (LSB) Data Bit 7 (MSB) ACK (A) R/W Bit 0 (LSB) Address Bit 1 Address Bit 7 (MSB) START condition (S) STOP condition (P) two bytes for read Input port register(1) 002aag952 tLOW tHIGH tr tf 0.7 × VDD 0.3 × VDD 0.7 × VDD 0.3 × VDD tSP tBUF tf tHD;STA tr SCL SDA tSU;DAT tHD;DAT tf(o) tVD;ACK tVD;DAT tVD;ACK tSU;STA tSU;STO 002aag804 repeat START condition STOP condition |
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