AD7709

–11–

REV. PrA

January 2001

PRELIMINARY TECHNICAL DATA

SF

Data Update

Input Range

Word

Rate (Hz)

±20mV

±40mV

±80mV

±160mV ±320mV ±640mV ±1.24V

±2.56V

13

105.3

1.50

1.50

1.60

1.75

3.50

4.50

6.70

11.75

69

19.79

0.60

0.65

0.65

0.65

0.65

0.95

1.40

2.30

255

5.35

0.35

0.35

0.37

0.37

0.37

0.51

0.82

1.25

ADC NOISE PERFORMANCE

Tables I and II below show the output rms noise and output peak-to-peak resolution in bits (rounded to the nearest

0.5LSB) for some typical output update rates . The numbers are typical and generated at a differential input voltage of

0V. The output update rate is selected via the SF7-SF0 bits in the Filter Register. It is important to note that the peak-

to-peak resolution figures represent the resolution for which there will be no code flicker within a six-sigma limit.The

output noise comes from two sources. The first is the electrical noise in the semiconductor devices (device noise) used in

the implementation of the modulator. Secondly, when the analog input is converted into the digital domain, quantization

noise is added. The device noise is at a low level and is independant of frequency. The quantization noise starts at an even

lower level but rises rapidly with increasing frequency to become the dominant noise source.The numbers in the tables are

given for the bipolar input ranges. For the unipolar ranges the rms noise numbers will be the same as the bipolar range

but the peak to peak resolution is now based on half the signal range which effectively means loosing 1 bit of resolution.

Table I. Typical Output RMS Noise vs. Input Range and Update Rate for AD7709

Output RMS Noise in µV

SF

Data Update

Input Range

Word

Rate (Hz)

±20mV

±40mV

±80mV

±160mV ±320mV ±640mV ±1.24V

±2.56V

13

105.3

12

13

14

15

15

15.5

16

16

69

19.79

13

14

15

16

16

16

16

16

255

5.35

14

15

16

16

16

16

16

16

Table II. Peak-to-Peak Resolution vs. Input Range and Update Rate for AD7709

Peak-to-Peak Resolution in Bits

AD7709 ON-CHIP REGISTERS

Both the AD7709 is controlled and configured via 4 on-chip registers as shown in figure 4 and described in more detail

in the following section. In the following descriptions, SET implies a logic 1 state and CLEARED implies a logic 0 state

unless otherwise stated.

0A 1 A0

DIN

DOUT

ADC Data Register

Filter Register

DIN

DOUT

Configuration Register(24-Bits)

DOUT

REGISTER

SELEC T

DECODER

Status Register

C om m unicatio ns R egister

DIN

DIN

DOUT

DOUT

0

OSC P D

STB Y

R/W

WE N

Figure 4. AD7709 On-Chip Registers