AD7731BN datasheet(38/44 Pages) AD

38 / 44 page

AD7731

–38–

REV. 0

The 8XC51 is configured in its Mode 0 serial interface mode.

Its serial interface contains a single data line. As a result, the

DATA OUT and DATA IN pins of the AD7731 should be

connected together. This means that the AD7731 must not be

configured for continuous read operation when interfacing to

the 8XC51. The serial clock on the 8XC51 idles high between

data transfers and, therefore, the POL input of the AD7731

should be hard-wired to a logic high. The 8XC51 outputs the

LSB first in a write operation while the AD7731 expects the

MSB first so the data to be transmitted has to be rearranged

before being written to the output serial register. Similarly, the

AD7731 outputs the MSB first during a read operation while

the 8XC51 expects the LSB first. Therefore, the data read into

the serial buffer needs to be rearranged before the correct data

word from the AD7731 is available in the accumulator.

SYNC

RESET

AD7731

POL

DATA OUT

DATA IN

SCLK

P3.0

P3.1

8XC51

DVDD

Figure 19. AD7731 to 8XC51 Interface

AD7731 to ADSP-2103/ADSP-2105 Interface

Figure 20 shows an interface between the AD7731 and the

ADSP-2105 DSP processor. In the interface shown, the

RDY

bit of the Status Register is again monitored to determine when

the Data Register is updated. The alternative scheme is to use

an interrupt driven system, in which case the

RDY output is

connected to the

IRQ2 input of the ADSP-2105. The RFS and

TFS pins of the ADSP-2105 are configured as active low out-

puts and the ADSP-2105 serial clock line, SCLK, is also config-

ured as an output. The POL pin of the AD7731 is hard-wired

low. Because the SCLK from the ADSP-2105 is a continuous

clock, the

CS of the AD7731 must be used to gate off the clock

once the transfer is complete. The

CS for the AD7731 is active

when either the

RFS or TFS outputs from the ADSP-2105 are

active. The serial clock rate on the ADSP-2105 should be lim-

ited to 3 MHz to ensure correct operation with the AD7731.

SYNC

RESET

AD7731

DATA OUT

DATA IN

SCLK

ADSP-2105

DVDD

RFS

TFS

POL

Figure 20. AD7731 to ADSP-2105 Interface

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