AD7856ARS datasheet(15/32 Pages) AD

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AD7856

–15–

REV. A

AUTO CAL ON

POWER-UP

AVDD DVDD

AIN(+)

AIN(–)

CREF1

CREF2

SLEEP

DIN

DOUT

SYNC

CONVST

AGND

DGND

CLKIN

SCLK

REFIN/REFOUT

AD7856

ANALOG

SUPPLY

+5V

0.1 F

10 F

DVDD

0.01 F

MASTER CLOCK

INPUT

CONVERSION

START INPUT

FRAME SYNC INPUT

SERIAL DATA

OUTPUT

0.1 F

CAL

0.01 F

INTERNAL/

EXTERNAL

REFERENCE

0V TO 4.096V

INPUT

6MHz/4MHz OSCILLATOR

SERIAL CLOCK

INPUT

285kHz/148kHz PULSE GENERATOR

CH1

CH2

CH3

CH4

OSCILLOSCOPE

OPTIONAL

EXTERNAL

REFERENCE

AD780/

REF-198

SERIAL DATA INPUT

CH5

PULSE GENERATOR

DATA GENERATOR

0.1 F

2 LEADING

ZEROS FOR

ADC DATA

470nF

Figure 10. Typical Circuit

CIRCUIT INFORMATION

The AD7856 is a fast, 14-bit single supply A/D converter. The

part requires an external 6 MHz/4 MHz master clock (CLKIN),

two CREF capacitors, a CONVST signal to start conversion and

power supply decoupling capacitors. The part provides the user

with track/hold, on-chip reference, calibration features, A/D

converter and serial interface logic functions on a single chip.

The A/D converter section of the AD7856 consists of a conven-

tional successive-approximation converter based around a ca-

pacitor DAC. The AD7856 accepts an analog input range of 0

to +VDD where the reference can be tied to VDD. The reference

input to the part is buffered on-chip.

A major advantage of the AD7856 is that a conversion can be

initiated in software as well as applying a signal to the

CONVST

pin. Another innovative feature of the AD7856 is self-calibration

on power-up, which is initiated having a 0.01

µF capacitor from

the

CAL pin to DGND, to give superior dc accuracy. The part

should be allowed 150 ms after power up to perform this auto-

matic calibration before any reading or writing takes place. The

part is available in a 24-pin SSOP package and this offers the

user considerable spacing saving advantages over alternative

solutions.

CONVERTER DETAILS

The master clock for the part must be applied to the CLKIN

pin. Conversion is initiated on the AD7856 by pulsing the

CONVST input or by writing to the control register and setting

the CONVST bit to 1. On the rising edge of

CONVST (or at

the end of the control register write operation), the on-chip

track/hold goes from track to hold mode. The falling edge of the

CLKIN signal that follows the rising edge of the

CONVST

signal initiates the conversion, provided the rising edge of

CONVST occurs at least 10 ns typically before this CLKIN

edge. The conversion cycle will take 20 CLKIN periods from

this CLKIN falling edge. If the 10 ns setup time is not met, the

conversion will take 21 CLKIN periods. The maximum speci-

fied conversion time is 3.5

µs (6 MHz) 5.25 µs (4 MHz) for the

AD7856. When a conversion is completed, the BUSY output

goes low, and then the result of the conversion can be read by

accessing the data through the serial interface. To obtain opti-

mum performance from the part, the read operation should not

occur during the conversion or 500 ns prior to the next

CONVST

rising edge. However, the maximum throughput rates are achieved

by reading/writing during conversion, and reading/writing during

conversion is likely to degrade the Signal to (Noise + Distor-

tion) by only 0.5 dBs. The AD7856 can operate at throughput

rates up to 285 kHz. For the AD7856 a conversion takes 21

CLKIN periods; two CLKIN periods are needed for the acqui-

sition time, giving a full cycle time of 3.66

µs (= 260 kHz, CLKIN

= 6 MHz). When using the software conversion start for maximum

throughput the user must ensure the control register write op-

eration extends beyond the falling edge of BUSY. The falling

edge of BUSY resets the

CONVST bit to 0 and allows it to be

reprogrammed to 1 to start the next conversion.

TYPICAL CONNECTION DIAGRAM

Figure 10 shows a typical connection diagram for the AD7856.

The AGND and DGND pins are connected together at the

device for good noise suppression. The

CAL pin has a 0.01

µF

capacitor to enable an automatic self-calibration on power-up.

The conversion result is output in a 16-bit word with two lead-

ing zeros followed by the MSB of the 14-bit result. Note that

after the AVDD and DVDD power-up the part will require 150 ms

for the internal reference to settle and for the automatic calibra-

tion on power-up to be completed.

For applications where power consumption is a major concern

the

SLEEP pin can be connected to DGND. See Power-Down

section for more detail on low power applications.

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