AD7891AS-2 datasheet(10/20 Pages) AD

10 / 20 page

AD7891

–10–

REV. A

CONVERTER DETAILS

The AD7891 is an eight-channel, high speed, 12-bit data acqui-

sition system. It provides the user with signal scaling, multi-

plexer, track/hold, reference, A/D converter and high speed

parallel and serial interface logic functions on a single chip. The

signal conditioning on the AD7891-1 allows the part to accept

analog input ranges of

±5 V or ±10 V when operating from a

single supply. The input circuitry on the AD7891-2 allows the

part to handle input signal ranges of 0 V to +2.5 V, 0 V to +5 V

and

±2.5 V again while operating from a single +5 V supply.

The part requires a +2.5 V reference which can be provided

from the part’s own internal reference or from an external refer-

ence source.

Conversion is initiated on the AD7891 either by pulsing the

CONVST input or by writing a logic 1 to the SWCONV bit of

the control register. When using the hardware

CONVST input,

the on-chip track/hold goes from track to hold mode and the

conversion sequence is started on the rising edge of the

CONVST

signal. When a software conversion start is initiated, an internal

pulse is generated which delays the track/hold acquisition point

and the conversion start sequence until the pulse is timed out.

This internal pulse is initiated (goes from low to high) whenever

a write to the AD7891 control register takes place with a 1 in

the SWCONV bit. It then starts to discharge and the track/hold

cannot go into hold and conversion cannot be initiated until the

pulse signal goes low.

The conversion clock for the part is internally generated and

conversion time for the AD7891 is 1.6

µs from the rising edge of

the hardware

CONVST signal. The track/hold acquisition time

for the AD7891-1 is 600 ns while the track/hold acquisition time

for the AD7891-2 is 400 ns. To obtain optimum performance

from the part, the data read operation should not occur during

the conversion or during 100 ns prior to the next conversion.

This allows the AD7891-1 to operate at throughput rates up to

454.5 kSPS and the AD7891-2 at throughput rates up to

500 kSPS in the parallel mode and achieve data sheet specifi-

cations. In the serial mode, the maximum achievable through-

put rate for both the AD7891-1 and the AD7891-2 is 357 kSPS

(assuming a 20 MHz serial clock).

All unused analog inputs should be tied to a voltage within the

nominal analog input range to avoid noise pickup. For mini-

mum power consumption, the unused analog inputs should be

tied to AGND.

INTERFACE INFORMATION

The AD7891 provides two interface options, a 12-bit parallel

interface and a high speed serial interface. The required inter-

face mode is selected via the MODE pin. The two interface

modes are discussed in the following sections.

Parallel Interface Mode

The parallel interface mode is selected by tying the MODE

input to a logic high. Figure 2 shows a timing diagram illustrating

the operational sequence of the AD7891 in parallel mode for a

hardware conversion start. The multiplexer address is written to

the AD7891 on the rising edge of the

WR input. The on-chip

track/hold goes into hold mode on the rising edge of

CONVST

and conversion is also initiated at this point. When the conversion

is complete, the end of conversion line (

EOC) pulses low to

indicate that new data is available in the AD7891’s output regis-

ter. This

EOC line can be used to drive an edge-triggered inter-

rupt of a microprocessor.

CS and RD going low accesses the

12-bit conversion result. In systems where the part is interfaced

to a gate array or ASIC, this

EOC pulse can be applied to the

CS and RD inputs to latch data out of the AD7891 and into the

gate array or ASIC. This means that the gate array or ASIC does

not need any conversion status recognition logic and it also elimi-

nates the logic required in the gate array or ASIC to generate

the read signal for the AD7891.

tCONV

VALID DATA

OUTPUT

VALID DATA

OUTPUT

t10

CONVST (I)

EOC (O)

CS (O)

WR (I)

RD (I)

DB0 - DB11

(I/O)

NOTE

I - INPUT

O = OUTPUT

Figure 2. Parallel Mode Timing Diagram

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