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AD8052ARM Datasheet(PDF) 12 Page - Analog Devices |
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AD8052ARM Datasheet(HTML) 12 Page - Analog Devices |
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12 / 16 page ![]() AD8051/AD8052/AD8054 –12– REV. B Overdrive Recovery Overdrive of an amplifier occurs when the output and/or input range are exceeded. The amplifier must recover from this over- drive condition. As shown in Figure 36, the AD8051/AD8052/ AD8054 recovers within 60 ns from negative overdrive and within 45 ns from positive overdrive. Figure 36. Overdrive Recovery Driving Capacitive Loads Consider the AD8051/AD8052 in a closed-loop gain of +1 with +VS = 5 V and a load of 2 k Ω in parallel with 50 pF. Figures 37 and 38 show its frequency and time domain responses, respec- tively, to a small-signal excitation. The capacitive load drive of the AD8051/AD8052/AD8054 can be increased by adding a low valued resistor in series with the load. Figures 39 and 40 show the effect of a series resistor on capacitive drive for varying voltage gains. As the closed-loop gain is increased, the larger phase margin allows for larger capacitive loads with less peak- ing. Adding a series resistor with lower closed-loop gains ac- complishes the same effect. For large capacitive loads, the frequency response of the amplifier will be dominated by the roll-off of the series resistor and the load capacitance. FREQUENCY – MHz 500 0.1 1 10 100 VS = +5V G = +1 RL = 2k CL = 50pF VO = 200mV p-p 8 6 4 2 0 2 4 6 8 10 Figure 37. AD8051/AD8052 Closed-Loop Frequency Response: CL = 50 pF 2.60 2.55 2.50 2.45 2.40 Figure 38. AD8051/AD8052 200 mV Step Response: CL = 50 pF VS = +5V 30% OVERSHOOT RS = 3 RS = 0 RG RF CL RS VOUT VIN 100mV STEP 50 10000 1000 1 16 2 345 100 10 A CL – V/V Figure 39. AD8051/AD8052 Capacitive Load Drive vs. Closed-Loop Gain VS = +5V 30% OVERSHOOT RG RF CL RS VOUT VIN 100mV STEP 50 RS = 10 RS = 0 A CL – V/V 1000 100 10 16 2 345 Figure 40. AD8054 Capacitive Load Drive vs. Closed-Loop Gain Circuit Description The AD8051/AD8052/AD8054 is fabricated on Analog Devices’ proprietary eXtra-Fast Complementary Bipolar (XFCB) pro- cess, which enables the construction of PNP and NPN transis- tors with similar fTs in the 2 GHz–4 GHz region. The process is dielectrically isolated to eliminate the parasitic and latch-up |
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