AD8327 datasheet(3/20 Pages) AD

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REV. 0

–3–

AD8327

LOGIC INPUTS (TTL/CMOS-Compatible Logic)

Parameter

Min

Typ

Max

Unit

Logic “1” Voltage

2.1

5.0

Logic “0” Voltage

0.8

Logic “1” Current (VINH = 5 V) CLK, SDATA, DATEN

020

Logic “0” Current (VINL = 0 V) CLK, SDATA, DATEN

–600

–100

Logic “1” Current (VINH = 5 V) TXEN

190

µA

Logic “0” Current (VINL = 0 V) TXEN

–250

–30

µA

Logic “1” Current (VINH = 5 V) SLEEP

190

µA

Logic “0” Current (VINL = 0 V) SLEEP

–250

–30

µA

TIMING REQUIREMENTS

Parameter

Min

Typ

Max

Unit

Clock Pulsewidth (tWH)

16.0

Clock Period (tC)

32.0

Setup Time SDATA vs. Clock (tDS)

5.0

Setup Time

DATEN vs. Clock (t

ES)

15.0

Hold Time SDATA vs. Clock (tDH)

5.0

Hold Time

DATEN vs. Clock (t

EH)

3.0

Input Rise and Fall Times, SDATA,

DATEN, Clock (t

R, tF)10

VALID DATA WORD G1

MSB. . . .LSB

GAIN TRANSFER (G1)

8 CLOCK

CYCLES

GAIN TRANSFER (G2)

OFF

ANALOG

OUTPUT

SIGNAL AMPLITUDE (p-p)

TXEN

CLK

SDATA

DATEN

VALID DATA WORD G2

Figure 2. Serial Interface Timing

VALID DATA BIT

MSB

MSB-1

MSB-2

SDATA

CLK

Figure 3. SDATA Timing

(Full Temperature Range, VCC = 5 V, tR = tF = 4 ns, fCLK = 8 MHz unless otherwise noted.)

(

DATEN, CLK, SDATA, TXEN, SLEEP, V

CC = 5 V: Full Temperature Range)

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