AD9772EB datasheet(17/32 Pages) AD

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REV. A

AD9772A

–17–

+1.2V REF

REFIO

FSADJ

CURRENT

SOURCE

ARRAY

250pF

REFLO

AVDD

AD9772A

0.1 F

ADDITIONAL

LOAD

OPTIONAL

EXTERNAL

REF BUFFER

2.7V TO 3.6V

Figure 15. Internal Reference Configuration

The internal reference can be disabled by connecting REFLO to

AVDD. In this case, an external 1.2 V reference such as the

AD1580 may then be applied to REFIO as shown in Figure 16.

The external reference may provide either a fixed reference

voltage to enhance accuracy and drift performance or a varying

reference voltage for gain control. Note that the 0.1

µF compen-

sation capacitor is not required since the internal reference is

disabled, and the high input impedance of REFIO minimizes

any loading of the external reference.

+1.2V REF

REFIO

FSADJ

CURRENT

SOURCE

ARRAY

250pF

REFLO

AVDD

AD9772A

AD1580

2.7V TO 3.6V

REFERENCE

CONTROL

AMPLIFIER

RSET

IREF =

VREFIO/RSET

10k

VREFIO

Figure 16. External Reference Configuration

REFERENCE CONTROL AMPLIFIER

The AD9772A also contains an internal control amplifier that is

used to regulate the DAC’s full-scale output current, IOUTFS.

The control amplifier is configured as a V-I converter, as shown

in Figure 16, such that its current output, IREF, is determined by

the ratio of the VREFIO and an external resistor, RSET, as stated in

Equation 4. IREF is copied to the segmented current sources with

the proper scaling factor to set IOUTFS as stated in Equation 3.

The control amplifier allows a wide (10:1) adjustment span of

IOUTFS over a 2 mA to 20 mA range by setting IREF between

62.5

µA and 625 µA. The wide adjustment span of IOUTFS

provides several application benefits. The first benefit relates

directly to the power dissipation of the AD9772’s DAC, which

is proportional to IOUTFS (refer to the Power Dissipation sec-

tion). The second benefit relates to the 20 dB adjustment, which

is useful for system gain control purposes.

IREF can be controlled using the single-supply circuit shown in

Figure 17 for a fixed RSET. In this example, the internal refer-

ence is disabled, and the voltage of REFIO is varied over its

compliance range of 1.25 V to 0.10 V. REFIO can be driven

by a single-supply DAC or digital potentiometer, thus allowing

IREF to be digitally controlled for a fixed RSET. This particular

example shows the AD5220, an 8-bit serial input digital potenti-

ometer, along with the AD1580 voltage reference. Note, since

the input impedance of REFIO does interact and load the

digital potentiometer wiper to create a slight nonlinearity in the

programmable voltage divider ratio, a digital potentiometer with

10 k

Ω or less of resistance is recommended.

+1.2V REF

REFIO

FSADJ

CURRENT

SOURCE

ARRAY

250pF

REFLO

AVDD

AD9772A

AD1580

2.7V TO 3.6V

RSET

10k

AD5220

1.2V

Figure 17. Single-Supply Gain Control Circuit

ANALOG OUTPUTS

The AD9772A produces two complementary current outputs,

IOUTA and IOUTB, which may be configured for single-ended or

differential operation. IOUTA and IOUTB can be converted into

complementary single-ended voltage outputs, VOUTA and

VOUTB, via a load resistor, RLOAD, as described in the DAC

Transfer Function section, by Equations 5 through 8. The

differential voltage, VDIFF, existing between VOUTA and VOUTB,

can also be converted to a single-ended voltage via a transformer

or differential amplifier configuration.

Figure 18 shows the equivalent analog output circuit of the

AD9772A, consisting of a parallel combination of PMOS differ-

ential current switches associated with each segmented current

source. The output impedance of IOUTA and IOUTB is determined

by the equivalent parallel combination of the PMOS switches

and is typically 200 k

Ω in parallel with 3 pF. Due to the nature

of a PMOS device, the output impedance is also slightly dependent

on the output voltage (i.e., VOUTA and VOUTB) and, to a lesser

extent, the analog supply voltage, AVDD, and full-scale current,

IOUTFS. Although the output impedance’s signal dependency can

be a source of dc nonlinearity and ac linearity (i.e., distortion), its

effects can be limited if certain precautions are noted.

IOUTA and IOUTB also have a negative and positive voltage compli-

ance range. The negative output compliance range of –1.0 V is

set by the breakdown limits of the CMOS process. Operation

beyond this maximum limit may result in a breakdown of the

output stage and affect the reliability of the AD9772A. The positive

output compliance range is slightly dependent on the full-scale

output current, IOUTFS. Operation beyond the positive compliance

range will induce clipping of the output signal, which severely

degrades the AD9772A’s linearity and distortion performance.

AD9772A

AVDD

IOUTA

RLOAD

IOUTB

Figure 18. Equivalent Analog Output Circuit

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