AD9774EB datasheet(15/24 Pages) AD

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AD9774

–15–

REV. B

DVDD

DIGITAL

INPUT

Figure 32. Equivalent Digital Input

Since the AD9774 is capable of being updated up to 32 MSPS,

the quality of the clock and data input signals are important in

achieving the optimum performance. Operating the AD9774

with reduced logic swings and a corresponding digital supply

(DVDD) will result in the lowest data feedthrough and on-chip

digital noise. The drivers of the digital data interface circuitry

should be specified to meet the minimum setup and hold times

of the AD9774 as well as its required min/max input logic level

thresholds.

Digital signal paths should be kept short and run lengths matched

to avoid propagation delay mismatch. The insertion of a low

value resistor network (i.e., 20

Ω to 100 Ω) between the AD9774

digital inputs and driver outputs may be helpful in reducing any

overshooting and ringing at the digital inputs that contribute to

data feedthrough.

The external clock driver circuitry should provide the AD9774

with a low jitter clock input meeting the min/max logic levels

while providing fast edges. Fast clock edges will help minimize

any jitter that will manifest itself as phase noise on a recon-

structed waveform. Thus, the clock input should be driven by

the fastest logic family suitable for the application.

SLEEP AND SNOOZE MODE OPERATION

The AD9774 has a SLEEP function that turns off the output

current and reduces the supply current to less than 5 mA over

the specified supply range of 2.7 V to 5.5 V and temperature

range. This mode can be activated by applying a logic level “1”

to the SLEEP pin. The AD9774 takes less than 0.1

µs to power

down and approximately 6.4

µs to power back up.

The SNOOZE mode should be considered as an alternative

power-savings option if the power-up characteristics of the

SLEEP mode are unsuitable. This mode, which is also activated

by applying a logic level “1” to the SNOOZE pin, disables the

AD9774’s digital filters only, resulting in significant power

savings. Both the SLEEP and SNOOZE pins should be tied to

DCOM if power savings is not required.

POWER DISSIPATION

The power dissipation, PD, of the AD9774 is dependent on

several factors, including: (1) AVDD, PLLVDD, and DVDD,

the power supply voltages; (2) IOUTFS, the full-scale current

output; (3) fCLOCK, the update rate; and (4) the reconstructed

digital input waveform. The power dissipation is directly pro-

portional to the analog supply current, IAVDD, and the digital

supply current, IDVDD. IAVDD is directly proportional to IOUTFS,

as shown in Figure 33, and is insensitive to fCLOCK.

Conversely, IDVDD is dependent on both the digital input wave-

form, fCLOCK, and digital supply DVDD. Figures 34 and 35

show IDVDD as a function of full-scale sine wave output ratios

(fOUT/fCLOCK) for various update rates with DVDD = 5 V and

DVDD = 3 V, respectively. Note, how IDVDD is reduced by more

than a factor of 2 when DVDD is reduced from 5 V to 3 V.

IOUTFS – mA

220

1012

141618

Figure 33. IAVDD vs. IOUTFS

RATIO –

fOUT/fCLOCK

200

180

0.01

1.0

0.10

100

140

120

160

32MSPS

16MSPS

8MSPS

4MSPS

Figure 34. IDVDD vs. Ratio @ DVDD = 5 V

RATIO –

fOUT/fCLOCK

100

0.01

1.0

0.10

32MSPS

16MSPS

8MSPS

4MSPS

Figure 35. IDVDD vs. Ratio @ DVDD = 3 V

For those applications requiring the AD9774 to operate under the

following conditions: (1) AVDD, PLLVDD and DVDD = +5 V;

(2) fCLOCK > 25 MSPS; and (3) ambient temperatures > 70°C;

proper thermal management via a heatsink or thermal epoxy is

recommended.

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