AD9832 datasheet(3/16 Pages) AD

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–3–

AD9832

REV. A

TIMING CHARACTERISTICS (V

DD = +3.3 V

10%; +5 V

10%; AGND = DGND = 0 V, unless otherwise noted)

Limit at

TMIN to TMAX

Parameter

(B Version)

Units

Test Conditions/Comments

ns min

MCLK Period

ns min

MCLK High Duration

ns min

MCLK Low Duration

ns min

SCLK Period

ns min

SCLK High Duration

ns min

SCLK Low Duration

ns min

FSYNC to SCLK Falling Edge Setup Time

ns min

FSYNC to SCLK Hold Time

SCLK – 5

ns max

ns min

Data Setup Time

t10

ns min

Data Hold Time

t11

ns min

FSELECT, PSEL0, PSEL1 Setup Time Before MCLK Rising Edge

t11A*

ns min

FSELECT, PSEL0, PSEL1 Setup Time After MCLK Rising Edge

*See Pin Function Descriptions.

Guaranteed by design but not production tested.

MCLK

Figure 2. Master Clock

SCLK

FSYNC

SDATA

t10

D15

D14

D15

D14

Figure 3. Serial Timing

t11A

t11

VALID DATA

MCLK

FSELECT

PSEL0, PSEL1

Figure 4. Control Timing

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