AD9856SLASHPCB datasheet(5/32 Pages) AD

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AD9856

–5–

REV. B

FUNCTIONAL BLOCK AND MODE DESCRIPTION

Operating Modes

1. Complex quadrature modulator mode.

2. Single tone output mode.

Input Data Format

Programmable: 12-bit, 6-bit, or 3-bit input formats. Data input to the AD9856 is

12-bit, twos complement. Complex I/Q symbol component data is required to be at

least 2

× oversampled, depending upon configuration.

Input Sample Rate

Up to 50 Msamples/s @ 200 MHz SYSCLK rate.

Input Reference Clock Frequency

For DC-80 MHz AOUT operation (200 MHz SYSCLK rate):

w/REFCLK Multiplier enabled: 10 MHz–50 MHz, programmable via control bus

w/REFCLK Multiplier disabled: 200 MHz.

Note: For optimum data synchronization, the AD9856 Reference Clock, and the

input data clock, should be derived from the same clock source.

Internal Reference Clock Multiplier

Programmable in integer steps over the range of 4

×–20×. Can be disabled (effective

REFCLK Multiplier = 1) via control bus. Output of REFCLK Multiplier = SYSCLK

rate, which is the internal clock rate applied to the DDS and DAC function.

Profile Select

Four pin-selectable, preprogrammed formats. Available for modulation and single

tone operating modes.

Interpolating Range

Fixed 4

×, selectable 2× and selectable 2×–63× range.

Half-Band Filters

Interpolating filters that provide upsampling and reduce the effects of the CIC

passband roll-off characteristics.

TxENABLE Function–Burst Mode

When Burst Mode is enabled via the control bus, the rising edge of the applied

TxENABLE pulse should be coincident with, and frame, the input data packet. This

establishes data sampling synchronization.

TxENABLE Function–Continuous Mode

When continuous mode is enabled via the control bus, the TxENABLE pin becomes

an I/Q control line. A Logic “1” on TxENABLE indicates I data is being presented

to the AD9856. A Logic “0” on TxENABLE indicates Q data is being presented to the

AD9856. Each rising edge of TxENABLE resynchronizes the AD9856 input sam-

pling capability.

Inverse SINC Filter

Precompensates for SIN(x)/x roll-off of DAC; user bypassable.

I/Q Channel Invert

× Cos(ωt) + Q × Sin(ωt)] or [I × Cos(ωt) – Q × Sin(ωt)] (default), configurable via

control bus, per profile.

Full Sleep Mode

Power dissipation reduced to less than 6 mW when Full Sleep Mode active, program-

mable via control bus.

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