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AD9887/PCB Datasheet(PDF) 34 Page - Analog Devices |
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AD9887/PCB Datasheet(HTML) 34 Page - Analog Devices |
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34 / 40 page  REV. 0 –34– AD9887 Table XXXVI. Active VSYNC Results Bit 5 (VSYNC Detect) Override AVS 00 0 10 1 X 1 Bit 2 in 12H AVS = 1 means Sync separator. AVS = 0 means VSYNC input. The override bit is in Register 12H, Bit 3. 12 7 AIO—Active Interface Override This bit is used to override the automatic interface selec- tion (Bit 3 in Register 11H). To override, set this bit to Logic 1. When overriding, the active interface is set via Bit 6 in this register. Table XXXVII. Active Interface Override Settings AIO Result 0 Autodetermines the Active Interface 1 Override, Bit 6 Determines the Active Interface The default for this register is 0. 12 6 AIS—Active Interface Select This bit is used under two conditions. It is used to select the active interface when the override bit is set (Bit 7). Alternately, it is used to determine the active interface when not overriding but both interfaces are detected. Table XXXVIII. Active Interface Select Settings AIS Result 0 Analog Interface 1 Digital Interface The default for this register is 0. 12 5 Active Hsync Override This bit is used to override the automatic Hsync selection (Bit 2 in Register 11H). To override, set this bit to Logic 1. When overriding, the active Hsync is set via Bit 4 in this register. Table XXXIX. Active Hsync Override Settings Override Result 0 Autodetermines the Active Interface 1 Override, Bit 4 Determines the Active Interface The default for this register is 0. 12 4 Active Hsync Select This bit is used under two conditions. It is used to select the active Hsync when the override bit is set (Bit 5). Alter- nately, it is used to determine the active Hsync when not overriding but both Hsyncs are detected. Table XL. Active HSYNC Select Settings Select Result 0 HSYNC Input 1 Sync-on-Green Input The default for this register is 0. 12 3 Active VSYNC Override This bit is used to override the automatic VSYNC selection (Bit 1 in Register 11H). To override, set this bit to Logic 1. When overriding, the active interface is set via Bit 2 in this register. Table XLI. Active VSYNC Override Settings Override Result 0 Autodetermines the Active VSYNC 1 Override, Bit 2 Determines the Active VSYNC The default for this register is 0. 12 2 Active VSYNC Select This bit is used to select the active VSYNC when the override bit is set (Bit 3). Table XLII. Active VSYNC Select Settings Select Result 0 VSYNC Input 1 Sync Separator Output The default for this register is 0. 12 1 COAST Select This bit is used to select the active COAST source. The choices are the COAST input pin or VSYNC. If VSYNC is selected, the additional decision of using the VSYNC input pin or the output from the sync separator needs to be made (Bits 3, 2). Table XLIII. COAST Select Settings Select Result 0 COAST Input Pin 1 VSYNC (See Above Text) The default for this register is 0. 12 0 PWRDN This bit is used to put the chip in full power-down. This powers down both interfaces. See the section on Power Management for details of which blocks are actually powered down. Note, the chip will be unable to detect incoming activity while fully powered-down. Table XLIV. Power-Down Settings Select Result 0 Power-Down 1 Normal Operation The default for this register is 1. |
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