ADF4106BCP datasheet(17/20 Pages) AD

17 / 20 page

REV. 0

ADF4106

–17–

ADF4106

V940ME03

FREF

OUT

CLK

DATA

1000pF

REFIN

NOTE

DECOUPLING CAPACITORS (0.1 F/10pF) ON AVDD, DVDD,

VP OF THE ADF4106 AND ON VCC OF THE V940ME03 HAVE

BEEN OMITTED FROM THE DIAGRAM TO AID CLARITY.

100pF

MUXOUT

LOCK

DETECT

RFINA

RFINB

100pF

1.5nF

20pF

100pF

1, 3, 4, 5, 7, 8,

9, 11, 12, 13

RSET

5.1k

6.2k

4.3k

100pF

Figure 7. Local Oscillator for LMDS Base Station

INTERFACING

The ADF4106 has a simple SPI-compatible serial interface for

writing to the device. SCLK, SDATA and LE control the data

transfer. When LE (Latch Enable) goes high, the 24 bits which

have been clocked into the input register on each rising edge of

SCLK will get transferred to the appropriate latch. See Figure 1

for the Timing Diagram and Table I for the Latch Truth Table.

The maximum allowable serial clock rate is 20 MHz. This means

that the maximum update rate possible for the device is 833 kHz

or one update every 1.2

µs. This is certainly more than adequate

for systems which will have typical lock times in hundreds of

microseconds.

ADuC812 Interface

Figure 8 shows the interface between the ADF4106 and the

ADuC812 microconverter. Since the ADuC812 is based on an

8051 core, this interface can be used with any 8051-based

microcontroller. The microconverter is set up for SPI Master

Mode with CPHA = 0. To initiate the operation, the I/O port

driving LE is brought low. Each latch of the ADF4106 needs a

24-bit word. This is accomplished by writing three 8-bit bytes

from the microconverter to the device. When the third byte has

been written the LE input should be brought high to complete

the transfer.

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