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ADG621 Datasheet(PDF) 5 Page - Analog Devices

Part # ADG621
Description  CMOS -5 V/ 5V 4 OHM DUAL SPST SWITCHES
PDF  12 Pages
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Manufacturer  AD [Analog Devices]
Direct Link  http://www.analog.com
Logo AD - Analog Devices

ADG621 Datasheet(HTML) 5 Page - Analog Devices

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REV. 0
ADG621/ADG622/ADG623
–5–
TERMINOLOGY
VDD
Most Positive Power Supply Potential.
VSS
Most Negative Power Supply in a Dual Supply Application. In single supply applications, this should be tied
to ground at the device.
GND
Ground (0 V) Reference
IDD
Positive Supply Current
ISS
Negative Supply Current
S
Source Terminal. May be an input or output.
D
Drain Terminal. May be an input or output.
IN
Logic Control Input
RON
Ohmic resistance between D and S.
∆RON
On resistance match between any two Channels i.e., RON max – RON min.
RFLAT(ON)
Flatness is defined as the difference between the maximum and minimum value of on resistance as measured
over the specified analog signal range.
IS (OFF)
Source Leakage Current with the switch “OFF.”
ID (OFF)
Drain Leakage Current with the switch “OFF.”
ID, IS (ON)
Channel Leakage Current with the switch “ON.”
VD (VS)
Analog Voltage on Terminals D, S.
VINL
Maximum Input Voltage for Logic “0.”
VINH
Minimum Input Voltage for Logic “1.”
IINL(IINH)
Input Current of the Digital Input
CS (OFF)
“OFF” Switch Source Capacitance
CD (OFF)
“OFF” Switch Drain Capacitance
CD, CS (ON)
“ON” Switch Capacitance
tON
Delay between applying the digital control input and the output switching on.
tOFF
Delay between applying the digital control input and the output switching off.
tBBM
“OFF” time or “ON” time measured between the 90% points of both switches, when switching from one
address state to another.
Charge Injection
A measure of the Glitch Impulse transfered from the Digital input to the Analog output during switching.
Crosstalk
A measure of unwanted signal that is coupled through from one channel to another as a result of parasitic
capacitance.
Off Isolation
A measure of unwanted signal coupling through an “OFF” switch.
Bandwidth
The frequency response of the “ON” switch.
Insertion Loss
The loss due to the ON resistance of the Switch.
PIN CONFIGURATION
10-Lead
SOIC
(RM-10)
TOP VIEW
(Not to Scale)
10
9
8
7
6
1
2
3
4
5
NC = NO CONNECT
D1
S1
GND
S2
IN1
VDD
ADG621/
ADG622/
ADG623
VSS
NC
D2
IN2



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