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ADM696AR Datasheet(PDF) 11 Page - Analog Devices |
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ADM696AR Datasheet(HTML) 11 Page - Analog Devices |
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11 / 12 page ![]() ADM696/ADM697 REV. 0 –11– This application also shows an optional, external transistor which may be used to provide in excess of 100 mA current on VOUT. When VCC is higher than VBATT, the BATT ON output goes low, providing 25 mA of base drive for the external PNP transistor. The maximum current available is dependent on the power rating of the external transistor. RAM Write Protection The ADM697 CEOUT line drives the Chip Select inputs of the CMOS RAM. CEOUT follows CEIN as long as LLIN is above the reset threshold. If LLIN falls below the reset threshold, CEOUT goes high, independent of the logic level at CEIN. This prevents the microprocessor from writing erroneous data into RAM dur- ing power-up, power-down, brownouts and momentary power interruptions. OUTLINE DIMENSIONS Dimensions shown in inches and (mm). 16-Pin Plastic DIP (N-16) 0.840 (21.33) 0.745 (18.93) 0.325 (8.25) 0.300 (7.62) 0.015 (0.381) 0.008 (0.204) 0.195 (4.95) 0.115 (2.93) PIN 1 0.280 (7.11) 0.240 (6.10) 9 1 6 1 8 0.210 (5.33) 0.200 (5.05) 0.125 (3.18) 0.022 (0.558) 0.014 (0.356) 0.100 (2.54) BSC SEATING PLANE 0.060 (1.52) 0.015 (0.38) 0.150 (3.81) 0.070 (1.77) 0.045 (1.15) 16-Pin Cerdip (Q-16) PIN 1 0.840 (21.34) MAX 0.060 (1.52) 0.015 (0.38) 0.015 (0.381) 0.008 (0.204) 0.150 (3.81) MIN 0.200 (5.08) MAX 0.022 (0.558) 0.014 (0.356) 0.100 (2.54) BSC 0.070 (1.78) 0.30 (0.76) PLANE SEATING 0.310 (7.87) 0.220 (5.59) 0.320 (8.13) 0.290 (7.37) 1 8 9 16 16-Lead SOIC (R-16) 0.019 (0.49) 0.05 (1.27) REF 0.104 (2.65) 0.012 (0.3) 0.413 (10.50) 0.419 (10.65) 0.042 (1.07) 0.013 (0.32) 0.030 (0.75) 0.299 (7.60) 1 8 9 16 |
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