ADP3153

–9–

REV. 0

The maximum rms current of the low side FET is:

LPEAK

0.5

= 8.41 Arms

dissipation. If we allow 5% of the maximum output power for

FET dissipation, the total dissipation will be:

Allocating two-thirds of the total dissipation for the high side

FET and one-third for the low side FET, the required minimum

FET resistances will be:

Ω

Ω

Note that there is a tradeoff between converter efficiency and

cost. Larger FETs reduce the conduction losses and allow higher

efficiency but lead to increased cost. If efficiency is not a major

concern the Fairchild MOSFET NDP6030L or International

Rectifier IRL3103 is an economical choice for both the high side

Ω

°C. The low side FET is turned on with

at least 10 V. The high side FET, however, is turned on with

only 12 V – 5 V = 7 V. If we check the typical output character-

istics of the device in the data sheet, we find that for an output

Ω. This value is only slightly

crease due to the reduced gate drive can be neglected. We have

est FET junction temperature of 140

°C by a R

using the graph in the data sheet. In our case:

°C is 1.7 × 14

= 24 m

Ω.

The high side FET dissipation is:

where the second term represents the turn-off loss of the FET.

provided by the ADP3153 is about 1 A.)

The low side FET dissipation is:

(Note that there are no switching losses in the low side FET.)

To remove the dissipation of the chosen FETs, proper heatsinks

should be used. The Thermalloy 6030 heatsink has a thermal

impedance of 13

°C/W with convection cooling. With this heat-

sink, the junction-to-ambient thermal impedance of the chosen

high side FET

θ

to-case) + 0.5 (case-to-heatsink) = 15.5

°C/W.

At full load and at 50

°C ambient temperature, the junction

temperature of the high side FET is:

A smaller heatsink may be used for the low side FET, e.g., the

Thermalloy type 7141 (

θ = 20.3°C/W). With this heatsink, the

All of the above calculated junction temperatures are safely

below the 175

°C maximum specified junction temperature of

the selected FET.

The maximum operating junction temperature of the ADP3153

is calculated as follows:

where

θ

θ

JA

is equal to 110

°C/W and I

follows:

The result is:

In continuous-inductor-current mode, the source current of the

more capacitors with low equivalent series resistance (ESR) and

adequate ripple-current rating must be connected across the

input terminals. The maximum rms current of the input bypass

capacitors is:

≈ [V

Let us select the FA-type capacitor with 2700

µF capacitance

and 10 V voltage rating. The ESR of that capacitor is 34 m

Ω

and the allowed ripple current at 100 kHz is 1.94 A. At 105

°C

we would need to connect at least four such capacitors in paral-

lel to handle the calculated ripple current. At 50

°C ambient,

however, the ripple current can be increased, so three capacitors

in parallel are adequate.

The ripple voltage across the three paralleled capacitors is:

140 mV p-p

To further reduce the effect of the ripple voltage on the system

supply voltage bus and to reduce the input-current di/dt to

below the recommended maximum of 0.1 A/

µs, an additional

small inductor (L > 1.7

µH @ 10 A) should be inserted between

the converter and the supply bus (see Figure 2).

Feedback Loop Compensation Design

To keep the peak-to-peak output voltage deviation as small as

possible, the low frequency output impedance (i.e., the output

resistance) of the converter should be made equal to the ESR of

the output capacitor. That can be achieved by having a single-pole

frequency coincides with the ESR zero of the output capacitor. A

nated by the parallel combination of a resistor and capacitor. The

required resistor value can be calculated from the equation:

36

× R

SENSE

g

m

145 k

Ω R

COMP

()

= R

E

Ω are charac-

teristic of the ADP3153. The calculated compensating resis-

tance is:

Ω