REV. A

ADP3159/ADP3179

–5–

100

100nF

1 F

100nF

12V

1.2V

4-BIT CODE

20

19

18

17

16

15

14

13

12

11

1

2

3

4

5

6

7

8

9

10

VID0

VID1

VID2

VID3

LRFB1

LRDRV1

CS–

GND

DRVH

DRVL

VCC

LRFB2

LRDRV2

COMP

CT

CS+

FB

NC

NC

PWRGD

AD820

+

ADP3159/

ADP3179

NC = NO CONNECT

Figure 1. Closed Loop Output Voltage Accuracy

Test Circuit

10nF

1 F

100nF

VCC

10nF

20

19

18

17

16

15

14

13

12

11

1

2

3

4

5

6

7

8

9

10

VID0

VID1

VID2

VID3

LRFB1

LRDRV1

CS–

GND

DRVH

DRVL

VCC

LRFB2

LRDRV2

COMP

CT

CS+

FB

NC

NC

PWRGD

+

ADP3159/

ADP3179

NC = NO CONNECT

Figure 2. Linear Regulator Output Voltage Accuracy

Test Circuit

THEORY OF OPERATION

The ADP3159 and ADP3179 use a current-mode, constant

off-time control technique to switch a pair of external N-channel

MOSFETs in a synchronous buck topology. Constant off-time

operation offers several performance advantages, including that no

slope compensation is required for stable operation. A unique

feature of the constant off-time control technique is that since

the off-time is fixed, the converter’s switching frequency is a

function of the ratio of input voltage to output voltage. The fixed

off-time is programmed by the value of an external capacitor

connected to the CT pin. The on-time varies in such a way

that a regulated output voltage is maintained as described below

in the cycle-by-cycle operation. The on-time does not vary under

fixed input supply conditions, and it varies only slightly as a func-

tion of load. This means that the switching frequency remains

fairly constant in a standard computer application.

Active Voltage Positioning

The output voltage is sensed at the CS– pin. A voltage error

voltage and a programmable reference voltage. The reference

voltage is programmed to between 1.3 V and 2.05 V by an inter-

nal 4-bit DAC that reads the code at the voltage identification

(VID) pins (Refer to Table I for output voltage vs. VID pin code

information). A unique supplemental regulation technique called

Analog Devices Optimal Positioning Technology (ADOPT)

adjusts the output voltage as a function of the load current so

that it is always optimally positioned for a load transient. Stan-

dard (passive) voltage positioning, sometimes recommended for

use with other architectures, has poor dynamic performance

which renders it ineffective under the stringent repetitive tran-

sient conditions specified in Intel VRM documents. Consequently,

such techniques do not allow the minimum possible number of

output capacitors to be used. ADOPT, as used in the ADP3159

and ADP3179, provides a bandwidth for transient response that

is limited only by parasitic output inductance. This yields opti-

mal load transient response with the minimum number of

output capacitors.

Cycle-by-Cycle Operation

During normal operation (when the output voltage is regulated),

the voltage error amplifier and the current comparator are the

main control elements. During the on-time of the high-side

MOSFET, the current comparator monitors the voltage between

the CS+ and CS– pins. When the voltage level between the two

pins reaches the threshold level, the DRVH output is switched to

ground, which turns off the high-side MOSFET. The timing

capacitor CT is then charged at a rate determined by the off-time

controller. While the timing capacitor is charging, the DRVL

output goes high, turning on the low-side MOSFET. When the

voltage level on the timing capacitor has charged to the upper

threshold voltage level, a comparator resets a latch. The output

of the latch forces the low-side drive output to go low and the

high-side drive output to go high. As a result, the low-side switch

is turned off and the high-side switch is turned on. The sequence

is then repeated. As the load current increases, the output volt-

age starts to decrease. This causes an increase in the output of

the voltage-error amplifier, which, in turn, leads to an increase

in the current comparator threshold, thus tracking the load current. To

prevent cross conduction of the external MOSFETs, feedback is

incorporated to sense the state of the driver output pins. Before

the low-side drive output can go high, the high-side drive output

must be low. Likewise, the high-side drive output is unable to

go high while the low-side drive output is high.

Power Good

The ADP3159 has an internal monitor that senses the output

voltage and drives the PWRGD pin of the device. This pin is an

open drain output whose high level (when connected to a pull-up

resistor) indicates that the output voltage has been within a

±20%

regulation band of the targeted value for more than 500 ms. The

PWRGD pin will go low if the output is outside the regulation

band for more than 500 ms.

Output Crowbar

An added feature of using an N-channel MOSFET as the syn-

chronous switch is the ability to crowbar the output with the same

MOSFET. If the output voltage is 20% greater than the targeted

value, the controller IC will turn on the lower MOSFET,

which will current-limit the source power supply or blow its fuse,

pull down the output voltage, and thus save the microprocessor

from destruction. The crowbar function releases at approximately

50% of the nominal output voltage. For example, if the output

is programmed to 1.5 V, but is pulled up to 1.85 V or above, the

crowbar will turn on the lower MOSFET. If in this case the output

is pulled down to less than 0.75 V, the crowbar will release,

allowing the output voltage to recover to 1.5 V if the fault

condition has been removed.