REV. 0

ADP3334

–7–

In order to have the lowest possible sensitivity of the output

voltage to temperature variations, it is important that the paral-

lel resistance of R1 and R2 is always 50 k

Ω.

RR

RR

k

12

12

50

×

+

=Ω

Also, for the best accuracy over temperature the feedback volt-

age should be set for 1.178 V:

VV

R

RR

FB

OUT

=×

+









2

12

FB pin due to loading by the internal PTAT current.

Combining the above equations and solving for R1 and R2 gives

the following formulas:

Rk

V

V

OUT

FB

150

=×

Ω

R

k

V

V

FB

OUT

2

50

1

=

−









Ω

Table I. Feedback Resistor Selection

)

R1(1% Resistor) (k

Ω) R2 (1% Resistor) (kΩ)

1.5

63.4

232

1.8

76.8

147

2.2

93.1

107

2.7

115

88.7

3.3

140

78.7

5

210

64.9

10

422

56.2

Thermal Overload Protection

The ADP3334 is protected against damage from excessive power

dissipation by its thermal overload protection circuit which limits

the die temperature to a maximum of 165

°C. Under extreme

conditions (i.e., high ambient temperature and power dissipation)

where die temperature starts to rise above 165

°C, the output

current is reduced until the die temperature has dropped to a

safe level. The output current is restored when the die tempera-

ture is reduced.

Current and thermal limit protections are intended to protect

the device against accidental overload conditions. For normal

operation, device power dissipation should be externally limited

so that junction temperatures will not exceed 150

°C.

Calculating Junction Temperature

Device power dissipation is calculated as follows:

The proprietary package used in the ADP3334 has a thermal

resistance of 86.6

°C/W, significantly lower than a standard

SOIC-8 package. Assuming a 4-layer board, the junction tem-

perature rise above ambient temperature will be approximately

equal to:

∆TW

C W

C

A

J

=×

=

0 900

86 6

77 9

..

/

.

oo

To limit the maximum junction temperature to 150

°C, maxi-

mum allowable ambient temperature will be:

Printed Circuit Board Layout Consideration

All surface mount packages rely on the traces of the PC board to

conduct heat away from the package.

In standard packages the dominant component of the heat resis-

tance path is the plastic between the die attach pad and the

individual leads. In typical thermally enhanced packages one or

more of the leads are fused to the die attach pad, significantly

decreasing this component. To make the improvement mean-

ingful, however, a significant copper area on the PCB must be

attached to these fused pins.

The patented thermal coastline lead frame design of the ADP3334

uniformly minimizes the value of the dominant portion of the

thermal resistance. It ensures that heat is conducted away by all

pins of the package. This yields a very low 86.6

°C/W thermal

resistance for an SOIC-8 package, without any special board

layout requirements, relying only on the normal traces connected

to the leads. This yields a 15% improvement in heat dissipation

capability as compared to a standard SOIC-8 package. The

thermal resistance can be decreased by, approximately, an addi-

tional 10% by attaching a few square cm of copper area to the

IN or OUT pins of the ADP3334 package.

It is not recommended to use solder mask or silkscreen on the

PCB traces adjacent to the ADP3334’s pins since it will increase

the junction-to-ambient thermal resistance of the package.

Shutdown Mode

Applying a TTL high signal to the shutdown (SD) pin or tying

it to the input pin, will turn the output OFF. Pulling SD down

to 0.4 V or below, or tying it to ground will turn the output ON.

In shutdown mode, quiescent current is reduced to much less

than 1

µA.