ADSP-2191M datasheet(26/52 Pages) AD

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ADSP-2191M

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Host Port ALE Mode Write Cycle Timing

Table 15 and Figure 14 describe Host port write operations in Address Latch Enable (ALE) mode. For more information on ACK,

Ready, ALE, and ACC mode selection, see the Host port modes description on page 8.

Table 15. Host Port ALE Mode Write Cycle Timing

Parameter

Min

Max

Unit

Switching Characteristics

tWHKS1

HWR Asserted to HACK Asserted (Setup, ACK Mode) First

Byte

5tHCLK+tNH

NH are peripheral bus latencies (n

tHCLK); these are internal DSP latencies related to the number of peripheral DMAs attempting to access DSP memory

at the same time.

tWHKS2

HWR Asserted to HACK Asserted (Setup, ACK Mode)2

2Measurement is for the second, third, or fourth byte of a host write transaction. The quantity of bytes to complete a host write transaction is dependent on

the data bus size (8 or 16 bits) and the data type (16 or 24 bits).

tWHKH

HWR Deasserted to HACK Deasserted (Hold, ACK Mode)

tWHS

HWR Asserted to HACK Asserted (Setup, Ready Mode)

tWHH

HWR Asserted to HACK Deasserted (Hold, Ready Mode)

First Byte

05tHCLK+tNH

Timing Requirements

tCSAL

HCMS or HCIOMS Asserted to HALE Asserted

0ns

tALPW

HALE Asserted Pulsewidth

tALCSW

HALE Deasserted to

HCMS or HCIOMS Deasserted

tWCSW

HWR Deasserted to HCMS or HCIOMS Deasserted

tALW

HALE Deasserted to

HWR Asserted

tWCS

HWR Deasserted (After Last Byte) to HCMS or

HCIOMS Deasserted (Ready for Next Write)

0ns

tHKWD

HACK Asserted to

HWR Deasserted (Hold, ACK Mode)

1.5

tAALS

Address Valid to HALE Deasserted (Setup)

tALAH

HALE Deasserted to Address Invalid (Hold)

tDWS

Data Valid to

HWR Deasserted (Setup)

tWDH

HWR Deasserted to Data Invalid (Hold)

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