ADV7129 datasheet(10/20 Pages) AD

10 / 20 page

ADV7129

–10–

REV. 0

SENSE

If any one or more of the analog outputs, IOG, IOR and IOB,

exceed the internal voltage reference level (due to absence of

CRT), SENSE is set to logic “1.” The SENSE output can drive

one CMOS load and can be used to determine the absence of a

CRT monitor.

CLOCK CONTROL CIRCUIT

The ADV7129 has an integrated clock control circuit. This cir-

cuit is capable of generating the internal clocking signals.

A lower frequency external clock generator is used by enabling

the onboard PLL. This fixed multiple PLL is used to speed up

LOADIN by a factor of 8. This onboard 8

× clock multiplier is

activated by setting Bit CR20 of Command Register 2 from

logic “0” to logic “1.” It must be set up after power-up.

MICROPROCESSOR (MPU) PORT

The ADV7129 supports a standard MPU interface. All the

functions of the part are controlled via this MPU port. Direct

access is gained to the address register and all the control regis-

ters as well as the cursor palette. The following sections de-

scribe the setup for reading and writing to all of the devices’

registers.

MPU Interface

The MPU interface consists of a bidirectional, 8-bit wide data-

bus and interface control signals R/W, CE, C1, C0. Two write

operations are required to set up the lower 8 bits and higher

2 bits of the Address Register.

The ADV7129 contains a number of onboard registers includ-

ing the Address Register, Command Registers and Gain Error

Registers. Control Lines C1-C0 determine whether the Address

the other registers are being accessed.

The R/W and CE control inputs allow read and write access.

All registers can to read and written to.

Power-On Reset

After power-up, the ADV7129 must be set to perform a reset

operation. This is achieved by resetting the PLL (a low to high

transition on Bit CR20 of Command Register 2). This initial-

izes the pixel port such that the pixel sequence ABCDEFGH

starts at A. This reset can be performed as the registers are be-

ing initialized. The Command Registers power up in an indeter-

minate state and must be set up for the required operation. The

power-on is activated when VAA goes from 0 V to 5 V. This is

active for 1

µs. The ADV7129 should not be accessed during

this period.

The MPU can write to or read from all of the ADV7129s’ regis-

ters. Figure 6 shows the Control Registers and C1-C0 Control

Input Truth Table. The read/write timing is controlled by the

and R/W inputs. The Address Register determines which

Control Register is being accessed.

The registers can be addressed directly by two write cycles to set

up the high and low bytes of Address Register and then by a

read or write cycle of the MPU.

(continued from page 1)

The ADV7129 supports 24-bit true-color formats where screen

resolution is the primary design goal. The individual Red,

Green and Blue pixel input ports allow true-color image rendi-

tion at resolutions of 2048

× 2048 × 24 bit.

The ADV7129 is capable of generating RGB video output sig-

nals that are compatible with RS-343A and RS-170 video stan-

dards, without requiring external buffering.

An internal voltage reference is also provided to simplify system

design.

The ADV7129 is fabricated in a +5 V CMOS process.

The ADV7129 is packaged in a 304-pin PQFP package.

CIRCUIT DETAILS AND OPERATION

Digital video or pixel data is latched into the ADV7129 over the

pixel port. The data is multiplexed and latched into the three 8-

bit digital-to-analog converters (DACs) and output as an RGB

video signal.

The ADV7129 can be broken into three sections for purposes of

clarity of explanation:

1. Pixel port and clock control circuit.

2. MPU port, registers and cursor.

3. Digital-to-analog converters and video outputs.

Pixel Port and Clock Circuits

The pixel port of the ADV7129 is directly interfaced to the

video/graphics pipeline of a computer graphics subsystem. It is

connected directly through a gate array to the video RAM of the

system’s frame buffer. The pixel port of the ADV7129 consists of:

Color Data:

RED, GREEN, BLUE

Pixel Controls:

HSYNC

, VSYNC, CSYNC, BLANK

The associated clocking signals for the pixel port include:

Clock Input

LOADIN

Clock Output

LOADOUT

Pixel Port (Color Data)

The ADV7129 has 192 color data inputs. This supports 24-bit

true color with 8:1 multiplexing.

Color data is always latched on the rising edge of LOADIN.

LOADOUT is generated internally by the ADV7129. The fre-

quency of LOADOUT is the internal clock frequency (PCLK)

divided by 8.

Other pixel data signals latched into the part by LOADIN in-

clude HSYNC, BLANK, VSYNC and CSYNC.

HSYNC

, VSYNC, CSYNC, BLANK

The BLANK and SYNC video control signals drive the analog

outputs to the blanking and sync levels respectively. These are

latched on the rising edge of LOADIN. The SYNC information

can be encoded onto any of the IOG, IOR or IOB analog out-

puts by setting Bits CR12, CR13 or CR14 of Command Regis-

ter 1 to logic “1.”

The SYNC information is ignored if Bits CR12, CR13 and

CR14 of Command Register 1 are set to logic “0.”

The SYNC and BLANK information can be decoded onto the

inverted outputs by setting CR10 and CR11 of Command

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