ADV7191 datasheet(43/69 Pages) AD

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ADV7190/ADV7191

–43–

REV. 0

OCR07

OCR06

OCR05

OCR04

OCR03

OCR02

OCR01

OCR00

OCR07

ZERO MUST BE

WRITTEN TO

THIS BIT

CLKOUT

PIN CONTROL

ENSABLED

DISABLED

OCR01

OCR06 – OCR04

ONE MUST BE

WRITTEN TO

THESE BITS

OCR03 – OCR02

ZERO MUST BE

WRITTEN TO

THESE BITS

OCR00

ZERO MUST BE

WRITTEN TO

THIS BIT

Figure 87. Output Clock Register (OCR)

BRIGHTNESS DETECT REGISTER

(Address (SR5–SR0) = 34H)

he Brightness Detect Register is an 8-bit-wide register used only

to read back data in order to monitor the brightness/darkness of

the incoming video data on a ﬁeld-by-ﬁeld basis. The brightness

information is read from the I

2C and based on this information,

the color controls or the gamma correction controls may be

adjusted.

The luma data is monitored in the active video area only. The

average brightness I

2C register is updated on the falling edge of

every

VSYNC signal.

OUTPUT CLOCK REGISTER (OCR 9–0)

(Address (SR4–SR0) = 35H)

he Output Clock Register is a 8-bit-wide register. Figure 87

shows the various operations under the control of this register.

OCR BIT DESCRIPTION

Reserved (OCR00)

A Logic 0 must be written to this bit.

CLKOUT Pin Control (OCR01)

This bit enables the CLKOUT pin when set to 1 and, therefore,

outputs a 54 MHz clock generated by the internal PLL. The

PLL and 4

× Oversampling have to be enabled for this control to

take effect, (MR61 = 0; MR16 = 1).

Reserved (OCR02–03)

A Logic 0 must be written to these bits.

Reserved (OCR04–06)

A Logic 1 must be written to these bits.

Reserved (OCR07)

A Logic 0 must be written to this bit.

ADV7191 Datasheet(PDF) 43 Page - Analog Devices

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