RT7276 datasheet(21/24 Pages) RICHTEK

21 / 24 page

RT7275/76

DS7275/76-00 January 2013

www.richtek.com

is a registered trademark of Richtek Technology Corporation.

Thermal Considerations

The maximum power dissipation depends on the thermal

resistance of the IC package and the PCB layout, the rate

of surrounding airflow, and the difference between the

junction and ambient temperatures. The maximum power

dissipation can be calculated by the following formula :

PD(MAX) = (TJ(MAX)

− TA) / θJA

where TJ(MAX) is the maximum junction temperature, TA is

the ambient temperature, and

θJA is the junction to ambient

thermal resistance.

For recommended operating condition specifications, the

maximum junction temperature is 125

°C. The junction to

ambient thermal resistance,

θJA, is layout dependent. For

the TSSOP-14 (Exposed Pad) package the thermal

resistance,

θJA, is 40°C/W on a standard JEDEC 51-7

four-layer thermal test board. For the WDFN-10L 3x3

package the thermal resistance,

θJA, is 60°C/W on a

standard JEDEC 51-7 four-layer thermal test board. These

standard thermal test layouts have a very large area with

long 2oz. copper traces connected to each IC pin and

very large, unbroken 1oz. internal power and ground planes.

Meeting the performance of the standard thermal test

board in a typical tiny board area requires wide copper

traces well-connected to the IC's backside pad leading to

exposed copper areas on the component side of the board

as well as good thermal vias from the backside pad

connecting to a wide inner-layer ground plane and, perhaps,

to an exposed copper area on the board's solder side.

Using the backside tab in this way, 40

°C/W is achievable

in a small area with either package.

The maximum power dissipation at TA = 25

°C can be

calculated by the following formulas:

PD(MAX) = (125

°C − 25°C) / (40°C/W) = 2.50W for

TSSOP-14 (Exposed Pad) package

PD(MAX) = (125

°C − 25°C) / (60°C/W) = 1.67W for

WDFN-10L 3x3 package

The maximum power dissipation depends on operating

ambient temperature for fixed TJ(MAX) and thermal

resistance,

θJA. The derating curves in Figure 6 allow the

designer to see the effect of rising ambient temperature

on the maximum power dissipation.

Figure 6. Derating Curve of Maximum Power Dissipation

0.0

0.5

1.0

1.5

2.0

2.5

3.0

100

125

Ambient Temperature (°C)

Four-Layer PCB

WDFN-10L3x3

TSSOP-14 (Exposed Pad)

Layout Considerations

Follow the PCB layout guidelines for optimal performance

of the RT7275/76.

Keep the traces of the main current paths as short and

wide as possible.

Put the input capacitor as close as possible to the device

pins (VIN and PGND).

The high-frequency switching node (SW) has large

voltage swings and fast edges and can easily radiate

noise to adjacent components. Keep its area small to

prevent excessive EMI, while providing wide copper

traces to minimize parasitic resistance and inductance.

Keep sensitive components away from the SW node or

provide ground traces between for shielding, to prevent

stray capacitive noise pickup.

Connect the feedback network to the output capacitors

rather than the inductor. Place the feedback components

near the FB pin.

The exposed pad, PGND, andGND should be connected

to large copper areas for heat sinking and noise

protection. Provide dedicated wide copper traces for the

power path ground between the IC and the input and

output capacitor grounds, rather than connecting each

of these individually to an internal ground plane.

Avoid using vias in the power path connections that have

switched currents (from CIN to PGND and CIN to VIN)

and the switching node (SW).

RT7276 Datasheet(PDF) 21 Page - Richtek Technology Corporation

RT7276 Datasheet(HTML) 21 Page - Richtek Technology Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24

Datasheet Download

Link URL