REV. 0

EVAL-AD1852EB

–5–

APPENDIX A

MODULE

IF_Logic

TITLE

‘AD1852 EVB Logic’

//===================================================================================

//

FILE:

1852ext.abl

//

REVISION DATE:

11-01-99 (comment revisions on 2-9-00)

//

REVISION BY:

Brian Wachob

//

REVISION:

3.0 (plus comments)

//

//

//

PREVIOUS FILE:

1852r9.abl, AD1852v8.abl

//

PREVIOUS DATE:

10-01-99

//

PREVIOUS REVISION:

2.0

//

//

ORIGINAL AUTHOR:

Larry Hurst

//

//

BOARD REV.:

This code is written for the “AD185_ REV 1” eval. boards

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(with, of course, an AD1852 DAC installed on the eval. board)

//

//

DESCRIPTION:

//

//

This chip selects between the External Data Interface header (J2) and the

//

onboard CS8414 DIR (U2) for the AD1852 DAC input signals, depending upon

//

the SPDIF/EXT switch position (S3).

When the DIR is the selected signal

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source the digital audio signals, SDATA, BCLK and LRCLK also appear at the

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external Data Interface header (J2) as outputs.

//

//

It also decodes the Interface Mode Switch(S5) and sets the interface mode

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pins for both the CS8414 DIR and the AD1852 DAC and corrects the CS8414

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output signals for LJ, RJ, and DSP modes, to match the signal requirements

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for the AD1852.

//

//

It also decodes signals from LabView SPI port control software so that it

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can correctly set the interface mode pins for the CS8414 and correctly

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format the CS8414 output signal for LJ, RJ, and DSP modes.

(This

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functionality is required when the SPI port is used to set the data format

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used by the DAC instead of setting it directly via the IDPM pins with the

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Interface Mode Switch, S5.)

//

//

It also decodes the Deemphasis control signal from the CS8414 (U2) and

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DEEMPH switch(S4), enables and buffers the output master clock and the

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VERF signal from the CS8414.

//

//

Finally, the CPLD buffers and drives the status LEDs.

//

//=============================================================================

LIBRARY ‘MACH’;

MACH_SLEW(FAST,2,MCLK:MCLKO);

DECLARATIONS

//

IF_Logic DEVICE ‘M4-64/32-15VC’;

“INPUTS

———————————————————————————————————

//

TDI, TCK, TMS

pin 4, 7, 26;

//JTAG I/P’s

SLCT_C, SLCT_B, SLCT_A

pin 15, 19, 14;

//Interface Mode Select

ISDATA, IMCLK, ILRCLK, IBCLK

pin 1, 5, 9, 10;

//DIR I/P’s

VERF, NPREEMPH, NDEEMPH

pin 44, 8, 13;

//DAC Control

SPDIF_EXT

pin 12;

//DAC Signal Source Select

ZR, ZL

pin 24, 34;

//DAC ZERO Signals

EMCLK

pin 27;

//External MCLK Input