LTC2940 datasheet(5/32 Pages) LINER

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LTC2945

2945f

Note 1: Stresses beyond those listed under Absolute Maximum Ratings

may cause permanent damage to the device. Exposure to any Absolute

Maximum Rating condition for extended periods may affect device

reliability and lifetime.

Note 2: All currents into pins are positive. All voltages are referenced to

ground, unless otherwise noted.

Note 3: An internal shunt regulator limits the INTVCC pin to a minimum of

5.9V. Driving this pin to voltages beyond 5.9V may damage the part. This

pin can be safely tied to higher voltages through a resistor that limits the

current below 35mA.

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

I2C INTERFACE TIMING (Note 5)

fSCL(MAX)

Maximum SCL Clock Frequency

400

kHz

tLOW

Minimum SCL Low Period

0.65

1.3

μs

tHIGH

Minimum SCL High Period

600

tBUF(MIN)

Minimum Bus Free Time Between Stop/Start

Condition

0.12

1.3

μs

tHD,STA(MIN)

Minimum Hold Time After (Repeated) Start

Condition

140

600

tSU,STA(MIN)

Minimum Repeated Start Condition Set-Up

Time

600

tSU,STO(MIN)

Minimum Stop Condition Set-Up Time

600

tHD,DATI(MIN)

Minimum Data Hold Time Input

–100

tHD,DATO(MIN)

Minimum Data Hold Time Output

300

600

900

tSU,DAT(MIN)

Minimum Data Set-Up Time

100

tSP(MAX)

Maximum Suppressed Spike Pulse Width

110

250

tRST

Stuck Bus Reset Time

SCL or SDAI Held Low

SCL, SDAI Input Capacitance

510

ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating

temperature range, otherwise specifications are at TA = 25°C. VDD is from 4V to 80V unless otherwise noted. (Note 2)

Note 4: Internal clamps limit the SCL and SDAI pins to a minimum of 5.9V.

Driving these pins to voltages beyond the clamp may damage the part. The

pins can be safely tied to higher voltages through resistors that limit the

current below 5mA.

Note 5: Guaranteed by design and not subject to test.

Note 6:

TUE

ACTUAL CODE

−IDEAL CODE

()

4096

×100%

where IDEAL CODE is derived from a straight line passing through Code 0

at 0V and Theoretical Code of 4096 at VFS.

Note 7: ΔSENSE is defined as VSENSE+ – VSENSE–

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