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ACT-D1M96S Datasheet(PDF) 7 Page - Aeroflex Circuit Technology |
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ACT-D1M96S Datasheet(HTML) 7 Page - Aeroflex Circuit Technology |
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7 / 14 page ![]() Aeroflex Circuit Technology SCD3369-1 REV C 5/31/00 Plainview NY (516) 694-6700 7 Table 3 — Data-Mask (DQM) Command Truth Table † Command ‡ State of Bank(s) DQML DQMU § (n) Data In (n) Data Out (n+2) Mnemonic — T = deac and B = deac X N/A Hi-Z — — T = actv and B = actv (no access operation) ¶ X N/A Hi-Z — Data-in enable T = Write or B = Write L V N/A ENBL Data-in mask T = Write or B = Write H M N/A MASK Data-out enable T = Write or B = Write L N/A V ENBL NOTES: † For execution of these commands on cycle n: - CKE (n) must be high, or -t CES and n CLE must be satisfied for clock suspend exit. CS(n), RAS(n), CAS(n), WE(n), and A0-A11 are don’t cares. ‡ All other unlisted commands are considered vendor-reserved commands or illegal commands. § DQML controlsDQ0-7, DQ16-23, DQ32-39, DQ48-55, DQ64-71, DQ80-87 and DQMU controls DQ8-15, DQ24-31, DQ40-47, DQ56-63, DQ72-79, and DQ88-95 . ¶ A bank is no longer in an access operation one cycle after the last data-out cycle of a read operation, and two cycles after the last data-in cycle of a write operation. Neither the PDE nor the HOLD command is allowed on the cycle immediately following the last data-in cycle of a write operation. Legend: n = CLK cycle number, L = Logic low, H = Logic high, X = Don’t care, either logic low or logic high, V = Valid, M = Masked input data, N/A = Not applicable, T = Bank T, B = Bank B, actv = Activated, deac = Deactivated, write = Activated and accepting data inputs on cycle n, read = Activated and delivering data outputs on cycle (n + 2) Table 4 — Serial 4-Word Burst Sequences INTERNAL COLUMN ADDRESS A1-A0, BA1-BA0 DECIMAL BINARY START 2ND 3RD 4TH START 2ND 3RD 4TH 0 1 2 3 00 01 10 11 1 2 3 0 01 10 11 00 2 3 0 1 10 11 00 01 3 0 1 2 11 00 01 10 Table 5 – Serial 8-Word Burst Sequences INTERNAL COLUMN ADDRESS A2-A0, BA2-BA0 DECIMAL BINARY START 2ND 3RD 4TH 5TH 6TH 7TH 8TH START 2ND 3RD 4TH 5TH 6TH 7TH 8TH 0 1 2 3 4 5 6 7 000 001 010 011 100 101 110 111 1 2 3 4 5 6 7 0 001 010 011 100 101 110 111 000 2 3 4 5 6 7 0 1 010 011 100 101 110 111 000 001 3 4 5 6 7 0 1 2 011 100 101 110 111 000 001 010 4 5 6 7 0 1 2 3 100 101 110 111 000 001 010 011 5 6 7 0 1 2 3 4 101 110 111 000 001 010 011 100 6 7 0 1 2 3 4 5 110 111 000 001 010 011 100 101 7 0 1 2 3 4 5 6 111 000 001 010 011 100 101 110 |
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