T7121-PL2 datasheet(21/68 Pages) AGERE

21 / 68 page

Lucent Technologies Inc.

Data Sheet

April 1997

T7121 HDLC Interface for ISDN (HIFI-64)

Functional Description (continued)

Transmitter FIFO

Data associated with multiple frames can be written to

the transmit FIFO by the controlling microprocessor.

However, all frames must be explicitly tagged with a

Transmit Frame Complete (TFC) bit (R1—B7) or a

Transmit Abort (TABT) bit (R1—B6) by writing to regis-

ter 1. The TFC is tagged onto the last byte of a frame

written into the transmitter FIFO. TFC instructs the

transmitter to end the frame by attaching the CRC and

closing ﬂag following the tagged byte. Once written, the

TFC cannot be changed by another write to R1. If TFC

is not written before the last data byte is read out for

transmission, an underrun occurs. When the FIFO is

empty, writing two data bytes to the FIFO before setting

TFC provides a minimum of eight CLKX periods to

write TFC. TABT (R1—B6) and TFC (R1—B7) should

never be set to 1 simultaneously. This causes the trans-

mitter to enter an invalid state requiring a transmitter

reset.

When the transmitter has completed a frame, with a

closing ﬂag or an abort sequence, the TDONE

(R15—B0) bit is set to 1. If TDIE (R14—B0) is 1 and no

other prior unacknowledged interrupt exists, the INT

pin transitions.

Sending 1-Byte Frames

Sending 1-byte frames with an empty transmit FIFO is

not recommended. If the FIFO is empty, writing two

data bytes to the FIFO before setting TFC provides a

minimum of eight CLKX periods to write TFC. When

one byte is written to the FIFO, TFC must be written

within 1 CLKX period to guarantee it is effective. Thus,

1-byte frames are subject to underrun aborts. One-byte

frames cannot be aborted with TABT. Placing the trans-

mitter in 1s idle mode (FLAGS, R0—B2 = 0) lessens

the frequency of underruns. If the transmit FIFO is not

empty, then 1-byte frames present no problem.

Transmitter Underrun

After writing a byte to the transmit queue, the user has

eight CLKX cycles in which to write the next byte before

a transmitter underrun occurs. An underrun occurs

when the transmitter has ﬁnished transmitting all the

bytes in the queue, but the frame has not yet been

closed by writing TFC. When a transmitter underrun

occurs, the abort sequence is sent at the end of the last

valid byte transmitted. A TDONE interrupt is generated,

and the transmitter reports an underrun abort in the

interrupt status register (R15—B2). The transmitter

enters forced idle (sending FLAGS or IDLES based

upon the value in R0—B2) until the interrupt status reg-

ister (R15) is read.

Using the Transmitter Status and Fill Level

The Transmitter-interrupt Level bits (R1—B[5—0]) allow

the user to instruct the T7121 to interrupt the host pro-

cessor whenever the transmitter has a predetermined

number of empty locations. The number of locations

selected determines the time between transmitter

empty (TE) interrupts. The transmitter status bits

(R2—B[6—0]) report the number of empty locations in

the transmitter FIFO. The bits are encoded in binary

with bit 0 the least signiﬁcant bit. Also found in register

2 is the Transmitter Empty Dynamic bit, TED (R2—B7).

This bit, like the TE interrupt bit, is set when the number

of empty locations is less than or equal to the pro-

grammed empty level. TED returns to 0 when the trans-

mitter is ﬁlled to above the programmed empty level.

Polled interrupt systems can use TED to determine

when they can write to the transmit FIFO.

Programming Note: After the transmitter is turned off,

a transmitter reset should be performed (TRES, R6, bit

5 = 1) before the transmitter is turned on. After the

receiver is turned off, a receiver reset should be per-

formed (RRES, R6, bit 4 = 1) before the receiver is

turned on. The transmitter and receiver should both be

reset individually (i.e., not at the same time) after any

concentration highway conﬁguration change. If TRES =

RRES = 1 at the same time, a full chip reset is per-

formed: all register bits are forced to their reset values.

Receiver FIFO

The receiver status is available in two ways. First, the

queue manager creates a Status of Frame (SF) byte for

each HDLC frame and stores this status byte in the

FIFO after the last data byte of the associated frame.

Thus, a frame containing 24 user data bytes results in

25 bytes present in the receive FIFO. The SF status

byte has the following format:

STATUS OF FRAME BYTE

BIT7

BIT6

BIT5

BIT4

BIT3

BIT2

BIT1

BIT0

0000

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