AD7658BSTZ datasheet(29/32 Pages) AD

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Data Sheet

AD7656/AD7657/AD7658

Rev. D | Page 29 of 32

APPLICATION HINTS

LAYOUT

The printed circuit board that houses the AD7656/AD7657/

AD7658 should be designed so that the analog and digital

sections are separated and confined to certain areas of the board.

At least one ground plane should be used. It could be common

or split between the digital and analog sections. In the case of

the split plane, the digital and analog ground planes should be

joined in only one place, preferably underneath the AD7656/

AD7657/AD7658, or at least as close as possible to each part.

If the AD7656/AD7657/AD7658 are in a system where multiple

devices require analog-to-digital ground connections, the con-

nection should still be made at only one point, a star ground

point, which should be established as close as possible to the

AD7656/AD7657/AD7658. Good connections should be made

to the ground plane. Avoid sharing one connection for multiple

ground pins. Individual vias or multiple vias to the ground

plane should be used for each ground pin.

Avoid running digital lines under the devices because doing so

couples noise onto the die. The analog ground plane should be

allowed to run under the AD7656/AD7657/AD7658 to avoid

noise coupling. Fast-switching signals like CONVST or clocks

should be shielded with digital ground to avoid radiating noise

to other sections of the board, and they should never run near

analog signal paths. Crossover of digital and analog signals

should be avoided. Traces on different but close layers of the

board should run at right angles to each other to reduce the

effect of feedthrough through the board.

The power supply lines to the AVCC, DVCC, VDRIVE, VDD, and VSS

pins on the AD7656/AD7657/AD7658 should use as large a

trace as possible to provide low impedance paths and reduce the

effect of glitches on the power supply lines. Good connections

should be made between the AD7656/AD7657/AD7658 supply

pins and the power tracks on the board; this should involve the

use of a single via or multiple vias for each supply pin.

Good decoupling is also important to lower the supply

impedance presented to the AD7656/AD7657/AD7658 and to

reduce the magnitude of the supply spikes. Decoupling ceramic

capacitors, typically 100 nF, should be placed on all of the power

supply pins, VDD, VSS, AVCC, DVCC, and VDRIVE. These decoupling

capacitors should be placed close to, ideally right up against,

these pins and their corresponding ground pins. Additionally,

low ESR 10 μF capacitors should be placed on each of the

supply pins. Avoid sharing these capacitors between pins. Use

big vias to connect the capacitors to the power and ground

planes. Use wide, short traces between the via and the capacitor

pad, or place the via adjacent to the capacitor pad to minimize

parasitic inductances. Recommended decoupling capacitors are

100 nF, low ESR, ceramic capacitors (Farnell 335-1816) and

10 μF, low ESR, tantalum capacitors (Farnell 197-130) for the

AVCC decoupling. A large tantalum decoupling capacitor should

be placed where the AVCC supply enters the board.

An alternative reduced decoupling arrangement is outlined in

the Typical Connection Diagram section. This decoupling

arrangement groups the AVCC supply pins into pairs and allows

the decoupling capacitors to be shared between the supply pairs.

Group the six AVCC core supply pins into three pairs, Pin 34 and

Pin 35, Pin 40 and Pin 41, and Pin 46 and Pin 47. Connect the

supply pins in each pair together; their location on the AD7656/

AD7657/AD7658 pin configuration easily facilitates this. For

the AD7656, decouple each pair with a 100 µF capacitor; for the

AD7657, decouple each pair with a 33 µF capacitor; for the

AD7658, decouple each pair with a 22 µF capacitor. For this

minimum decoupling configuration, all other supply and

reference pins should be decoupled with a 10 µF decoupling

capacitor.

POWER SUPPLY CONFIGURATION

As outlined in the Absolute Maximum Ratings section, the

analog inputs should not be applied to the AD7656/AD7657/

AD7658 until after the AD7656/AD7657/AD7658 power

supplies have been applied to the device. However, if a

condition exists where the system analog signal conditioning

circuitry supplies are different to the VDD and VSS supplies of

the AD7656/AD7657/AD7658, or if the analog inputs may be

applied prior to the AD7656/AD7657/AD7658 supplies being

established, then an analog input series resister and Schottky

diodes in series with the VDD and VSS supplies are recom-

mended, see Figure 36. This configuration should also be

used if AVCC is applied to the AD7656/AD7657/AD7658

prior to VDD and VSS.

VDD

VSS

VDD

240Ω

ANALOG

INPUTS

AD7656/

AD7657/

AD7658

Figure 36. Power Supply Configuration

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