MPC2605ZP66 datasheet(13/30 Pages) MOTOROLA

13 / 30 page

MPC2605

MOTOROLA

MEMORY COHERENCE

When a processor brings data into its on–chip cache and

modifies it, a situation has arisen in which the main memory

now contains irrelevant, or stale, data. Given that most sys-

tems support some form of DMA there must exist a means by

which the processor is forced to write this modified, or dirty,

data back to main memory. The DMA bridge is responsible

for generating bus transactions to ensure that main memory

locations accessed by DMA operations do not contain stale

data. These transactions, called snoops, come in three dif-

ferent categories, each of which will be discussed below.

Snoops cause the processor and the MPC2605 to check

to see if they have dirty copies of the memory location speci-

fied in the snoop transaction. If either device does have a

dirty copy it will assert ARTRY and make use of the opportu-

nity presented in the BR window to write this data back to

main memory.

Situations can arise where a cache line is dirty in both the

processor’s L1 cache and in the MPC2605. In cases such as

these, snoop transactions should cause the processor to

write its data back to memory since it is by definition more

recent than the data in the MPC2605. Since ARTRY is a

shared signal and it cannot be determined which devices are

driving it, the MPC2605 samples CPU BR in the BR window

to determine if the snoop hit a dirty line in the L1 cache. If

CPU BR is asserted during this window, the MPC2605 will

defer to the processor.

Snoop Reads

A snoop read causes dirty data to be written back to

memory but allows both the L1 and L2 to keep a valid copy.

In cases where the snoop hits a dirty cache line in the pro-

cessor, the MPC2605 will update its contents as the proces-

sor writes the data back to main memory.

Snoop reads can be implemented in two ways. One is that

the DMA bridge can issue a clean transaction (TT[0:4] =

00000). The other is that the DMA bridge can do a read

transaction (TT[0:4] = x1010). If the DMA bridge does a read

transaction, the MPC2605 determines that it is a snoop read

rather than a processor read by the state of CPU BG the

cycle before TS was asserted. If the processor was not

granted the bus then the transaction had to have been is-

sued by the DMA bridge and is therefore a snoop read.

Snoop Writes

Snoop writes also cause dirty data to be written back to

main memory. The difference from a snoop read is that the

cache line must then be invalidated in both the processor’s

cache and in the L2 cache. When the processor writes data

back to memory in response to a snoop write, the MPC2605

will not cache the data as it appears on the bus. If a valid

copy resides in the cache, the MPC2605 will invalidate it.

Again there are multiple transactions that can be used by

the DMA bridge to implement a snoop write. It can issue a

flush transaction (TT[0:4] = 00100), a read with intent to

modify (TT[0:4] = x1110), or a write with flush (TT[0:4]

= 00010). As with snoop reads, the MPC2605 distinguishes

between processor issued data transactions and snoop

transactions by the state of CPU BG in the cycle previous to

the assertion of TS.

Snoop Kills

Kills are snoops that cause cache entries to be immedi-

ately invalidated, regardless of whether they are dirty. This

saves time if the DMA operation is going to modify all the

data in the cache line. To implement a snoop kill the DMA

bridge can issue a kill transaction (TT[0:4] = 01100) or a write

with kill (TT[0:4] = 00110).

TWO/FOUR CHIP IMPLEMENTATION

Multiple Castouts

Because each MPC2605 has its own castout buffer

(COB), it is possible for situations to arise in which more than

one device needs to do a copyback operation. Under normal

circumstances each device will enter castout conditions at

different times. In these cases, when a device determines

that it needs to do a castout, the L2 BR signal is first

sampled. If L2 BR is already asserted then it is clear that

another device is also in a castout situation. The late device

will wait until L2 BR is negated before continuing in its at-

tempt to perform its castout.

Because of the BR window protocol associated with asser-

tions of ARTRY, it is possible for a situation to arise where

device two is waiting for device one to do its castout before

asserting L2 BR. If there is an assertion of ARTRY by a de-

vice other than device one, device one is required to negate

L2 BR in the BR window. In order to prevent device two from

interpreting device one’s negation of L2 BR as an indication

that device one has completed its castout, a simple arbitra-

tion mechanism is used. All devices have a simple two–bit

counter that is synchronized such that all counters always

have the same value. For the purposes of performing a cast-

out operation, a given pair can only assert L2 BR if the count-

er is equal to its value of CFG[1:2]. This simple mechanism

prevents more than one device from asserting L2 BR in the

same cycle and therefore not being cognizant of the another

device’s need to perform a castout.

Snoop Hit Before Castout

The other situation that can cause problems with a shared

bus request occurs when a snoop hits a dirty line in one of

the MPC2605 devices. If device one has a cache line in its

COB, it will assert L2 BR so that it may perform a castout

operation. If a snoop hits a dirty line in device two, it will as-

sert both ARTRY and L2 BR so that it can write the snoop

data back to main memory. When device one detects that

ARTRY has been asserted, it needs to be made aware that

device two needs to request the bus. Otherwise, at the same

time that device two is asserting L2 BR, device one will at-

tempt to conform to the BR window protocol and negate

L2 BR. This situation is avoided by device one sampling FDN

when it detects that ARTRY has been asserted. If FDN is

asserted at the same time as ARTRY is asserted, device one

will recognize that device two is asserting ARTRY. device

one will then high–Z L2 BR so that there will not be conten-

tion when device two is asserting L2 BR.

MULTIPROCESSING

The MPC2605 can be used as a common cache for up to

four processors. For each processor there is a bus request,

bus grant, and data bus grant signal pin on the MPC2605.

Each of these pins needs to be connected to the respective

processor’s arbitration signals in the system.

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