MPC903 MPC904 MPC905

MOTOROLA

TIMING SOLUTIONS

BR1333 — REV 5

4

BCLK0–4

BCLK5

ENABLE2

ENABLE1

Figure 3. Enable Timing Diagram

APPLICATIONS INFORMATION

Driving Transmission Lines

The MPC903/904/905 clock driver was designed to drive

high speed signals in a terminated transmission line

environment. To provide the optimum flexibility to the user the

output drivers were designed to exhibit the lowest impedance

possible. With an output impedance of less than 10

Ω the

drivers can drive either parallel or series terminated

transmission lines. For more information on transmission

lines the reader is referred to application note AN1091 in the

Timing Solutions brochure (BR1333/D).

In most high performance clock networks point–to–point

distribution of signals is the method of choice. In a

point–to–point scheme either series terminated or parallel

terminated transmission lines can be used. The parallel

technique terminates the signal at the end of the line with a

50

Ω resistance to VCC/2. This technique draws a fairly high

level of DC current and thus only a single terminated line can

be driven by each output of the MPC903/904/905 clock

driver. For the series terminated case however there is no DC

current draw, thus the outputs can drive multiple series

terminated lines. Figure 4 illustrates an output driving a

single series terminated line vs two series terminated lines in

parallel. When taken to its extreme the fanout of the

MPC903/904/905 clock driver is effectively doubled due to its

capability to drive multiple lines.

Figure 4. Single versus Dual Transmission Lines

7

Ω

IN

MPC903

OUTPUT

BUFFER

RS = 43Ω

ZO = 50Ω

OutA

7

Ω

IN

MPC903

OUTPUT

BUFFER

RS = 43Ω

ZO = 50Ω

OutB0

RS = 43Ω

ZO = 50Ω

OutB1

The waveform plots of Figure 5 show the simulation

results of an output driving a single line vs two lines. In both

cases the drive capability of the MPC903/904/905 output

buffers is more than sufficient to drive 50

Ω transmission lines

on the incident edge. Note from the delay measurements in

the simulations a delta of only 43ps exists between the two

differently loaded outputs. This suggests that the dual line