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MPC930 Datasheet(PDF) 2 Page - Motorola, Inc |
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MPC930 Datasheet(HTML) 2 Page - Motorola, Inc |
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2 / 14 page ![]() MPC930 MPC931 MOTOROLA TIMING SOLUTIONS BR1333 — Rev 6 2 ÷2 ÷4 ÷2 ÷4 ÷4 ÷6 FUNCTION TABLES TCLK_Sel Reference 0 1 xtal (PECL_CLK) TCLK PLL_En PLL Status 0 1 Test Mode PLL Enabled ExtFB_Sel Reference 0 1 Int. ÷8 Ext_FB GNDO Qa1 Qa0 VCCO Div_Sela Div_Selb Div_Selc NC GNDO Qc1 Qc0 VCCO Ext_FB Shut_Dn1 Shut_Dn0 NC 25 26 27 28 29 30 31 32 15 14 13 12 11 10 9 12 345678 24 23 22 21 20 19 18 17 16 MPC930/ MPC931 Power_Dn PLL Status 0 1 VCO/1 VCO/2 Div_Sela,b,c 0 1 Qa Qb Qc Shut_Dn1 0 0 1 1 Div_Seln Qb & Qc Low, Qa Toggle Qa & Qb Low, Qc Toggle Qb Low, Qa & Qc Toggle All Toggle Shut_Dn0 0 1 0 1 Figure 1. 32–Lead Pinout (Top View) Figure 2. Logic Diagram POWER–ON RESET VCO PHASE DETECTOR LPF ÷8 MR/Tristate xtal OSC Shut_Dn1 Shut_Dn0 xtal2 xtal1 PLL_En Qa0 Qb0 Qb1 Power_Dn ÷2/÷4 ÷2/÷4 ÷4/÷6 Qc0 Qc1 DISABLE LOGIC Div_Selb Div_Sela Qa1 TCLK TCLK_Sel Ext_FB ExtFB_Sel Div_Selc MPC930 PECL_CLK PECL_CLK MPC931 MR/Tristate PLL Status 0 1 Disabled Enabled (Pullup) (Pullup) (Pulldown) (Pullup) (Pullup) (Pulldown) (Pulldown) (Pulldown) (Pullup) (Pullup) (Pulldown) (Pullup) (Pullup) (None) ÷2 |
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