AFS1500-FGG484 datasheet(49/334 Pages) MICROSEMI

49 / 334 page

Fusion Family of Mixed Signal FPGAs

Revision 4

2-33

Real-Time Counter System

The RTC system enables Fusion devices to support standby and sleep modes of operation to reduce

power consumption in many applications.

•

Sleep mode, typical 10 µA

•

Standby mode (RTC running), typical 3 mA with 20 MHz

The RTC system is composed of five cores:

•

RTC sub-block inside Analog Block (AB)

•

Voltage Regulator and Power System Monitor (VRPSM)

•

Crystal oscillator (XTLOSC); refer to the "Crystal Oscillator" section in the Fusion Clock

Resources chapter of the Fusion FPGA Fabric User’s Guide for more detail.

•

Crystal clock; does not require instantiation in RTL

•

1.5 V voltage regulator; does not require instantiation in RTL

All cores are powered by 3.3 V supplies, so the RTC system is operational without a 1.5 V supply during

standby mode. Figure 2-27 shows their connection.

Notes:

1. Signals are hardwired internally and do not exist in the macro core.

2. User is only required to instantiate the VRPSM macro if the user wishes to specify PUPO behavior of the voltage regulator

to be different from the default, or employ user logic to shut the voltage regulator off.

Figure 2-27 • Real-Time Counter System (not all the signals are shown for the AB macro)

VRPU

PTBASE1

PTEM1

PUB

VRINITSTATE

RTCPSMMATCH

FPGAGOOD

PUCORE

VREN1

VRPSM

1.5 Voltage Regulator

RTCXTLSEL

RTCMATCH

RTCPSMMATCH

XTLOSC

Real-Time Counter

XTAL1

XTAL2

CLKOUT

RTC_MODE[1:0]

SELMODE

RTCCLK

External

Pass

Transistor

2N2222

3.3 V

Power-Up/-Down

Toggle Control

Switch

1.5 V

TRST1

External Pin

Internal Pin

Can Be Route

to PLL

RTCXTLMODE[1:0]

Cores do not require any

RTL instantiation

Cores require RTL instantiation2

Sub-block in cores does not

require additional RTL instantiation

XTL

XTL1

Crystal Clock

MODE[1:0]

FPGA_EN1

AFS1500-FGG484 Datasheet(PDF) 49 Page - Microsemi Corporation

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