Forward Voltage, V - V

F

0.2

0.3

0.4

0.5

1

0.01

0.1

T = 125°C

J

25°C

75°C

-40°C

Forward Voltage, V - V

F

0.2

0.1

0.3

0.4

0.5

1

0.01

0.1

T = 100°C

J

75°C

25°C

-25°C

0°C

SN6501

SLLSEA0E – FEBRUARY 2012 – REVISED JANUARY 2013

www.ti.com

Table 1. Required maximum LDO Input Voltages for Various Push-pull Configurations

PUSH-PULL CONVERTER

LDO

CONFIGURATION

TURNS-RATIO

3.6

1.5 ± 3%

5.6

6 to 10

3.6

2.2 ± 3%

8.2

10

5.5

1.5 ± 3%

8.5

10

DIODE SELECTION

A rectifier diode should always possess low-forward voltage to provide as much voltage to the converter output

as possible. When used in high-frequency switching applications, such as the SN6501 however, the diode must

also possess a short recovery time. Schottky diodes meet both requirements and are therefore strongly

recommended in push-pull converter designs. An excellent choice for low-volt applications is the MBR0520L with

a typical forward voltage of 275 mV at 100 mA forward current. For higher output voltages such as ±10 V and

above use the MBR0530 which provides a higher DC blocking voltage of 30 V.

Figure 49. Diode Forward Characteristics for MBR0520L (left) and MBR0530 (right)

CAPACITOR SELECTION

The capacitors in the converter circuit in Figure 52 are multi-layer ceramic chip (MLCC) capacitors.

As with all high speed CMOS ICs, the SN6501 requires a bypass capacitor in the range of 10 nF to 100 nF.

The input bulk capacitor at the center-tap of the primary supports large currents into the primary during the fast

switching transients. For minimum ripple make this capacitor 10

μF to 22 μF. In a 2-layer PCB design with a

dedicated ground plane, place this capacitor close to the primary center-tap to minimize trace inductance. In a 4-

supply entrance of the board. To ensure low-inductance paths use two vias in parallel for each connection to a

reference plane or to the primary center-tap.

The bulk capacitor at the rectifier output smoothes the output voltage. Make this capacitor 10

μF to 22 μF.

The small capacitor at the regulator input is not necessarily required. However, good analog design practice

suggests, using a small value of 47 nF to 100 nF improves the regulator’s transient response and noise rejection.

The LDO output capacitor buffers the regulated output for the subsequent isolator and transceiver circuitry. The

choice of output capacitor depends on the LDO stability requirements specified in the data sheet. However, in

most cases, a low-ESR ceramic capacitor in the range of 4.7

μF to 10 μF will satisfy these requirements.

16

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