PIC16F87 datasheet(117/230 Pages) MICROCHIP

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 2002-2013 Microchip Technology Inc.

DS30487D-page 117

PIC16F87/88

12.1

A/D Acquisition Requirements

For the A/D converter to meet its specified accuracy, the

charge holding capacitor (CHOLD) must be allowed to

fully charge to the input channel voltage level. The ana-

log input model is shown in Figure 12-2. The source

impedance (RS) and the internal sampling switch (RSS)

impedance directly affect the time required to charge the

capacitor CHOLD. The sampling switch (RSS) impedance

varies over the device voltage (VDD), see Figure 12-2.

The maximum recommended impedance for analog

sources is 10 k

. As the impedance is decreased, the

acquisition time may be decreased. After the analog

input channel is selected (changed), this acquisition

must be done before the conversion can be started.

calculate

the

minimum

acquisition

time,

Equation 12-1 may be used. This equation assumes

that 1/2 LSb error is used (1024 steps for the A/D). The

1/2 LSb error is the maximum error allowed for the A/D

to meet its specified resolution.

To calculate the minimum acquisition time, TACQ, see

the “PIC® Mid-Range MCU Family Reference Manual”

(DS33023).

EQUATION 12-1:

ACQUISITION TIME

FIGURE 12-2:

ANALOG INPUT MODEL

TACQ

Amplifier Settling Time + Hold Capacitor Charging Time + Temperature Coefficient

TAMP + TC + TCOFF

s + TC + [(Temperature -25°C)(0.05 s/°C)]

CHOLD (RIC + RSS + RS) In(1/2047)

-120 pF (1 k

 + 7 k + 10 k) In(0.0004885)

16.47

s

s + 16.47 s + [(50°C – 25C)(0.05 s/C)

19.72

s

Note 1: The reference voltage (VREF) has no effect on the equation, since it cancels itself out.

2: The charge holding capacitor (CHOLD) is not discharged after each conversion.

3: The maximum recommended impedance for analog sources is 10 k

. This is required to meet the pin

leakage specification.

4: After a conversion has completed, a 2.0 TAD delay must complete before acquisition can begin again.

During this time, the holding capacitor is not connected to the selected A/D input channel.

CPIN

ANx

5 pF

VDD

VT = 0.6V

ILEAKAGE

RIC

 1K

Sampling

Switch

SS RSS

CHOLD

= DAC Capacitance

VSS

Sampling Switch

567 8 9 10 11

)

VDD

= 120 pF

±500 nA

Legend: CPIN

ILEAKAGE

RIC

CHOLD

= Input Capacitance

= Threshold Voltage

= Leakage Current at the pin due to

= Interconnect Resistance

= Sampling Switch

= Sample/Hold Capacitance (from DAC)

various junctions

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