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PIC16F87 Datasheet(PDF) 134 Page - Microchip Technology |
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PIC16F87 Datasheet(HTML) 134 Page - Microchip Technology |
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134 / 230 page ![]() PIC16F87/88 DS30487D-page 134 2002-2013 Microchip Technology Inc. 15.8 Time-out Sequence On power-up, the time-out sequence is as follows: the PWRT delay starts (if enabled) when a POR occurs. Then, OST starts counting 1024 oscillator cycles when PWRT ends (LP, XT, HS). When the OST ends, the device comes out of Reset. If MCLR is kept low long enough, all delays will expire. Bringing MCLR high will begin execution immediately. This is useful for testing purposes, or to synchronize more than one PIC16F87/88 device operating in parallel. Table 15-3 shows the Reset conditions for the STATUS, PCON and PC registers, while Table 15-4 shows the Reset conditions for all the registers. 15.9 Power Control/Status Register (PCON) The Power Control/Status Register, PCON, has two bits to indicate the type of Reset that last occurred. Bit 0 is Brown-out Reset Status bit, BOR. Bit BOR is unknown on a Power-on Reset. It must then be set by the user and checked on subsequent Resets to see if bit BOR cleared, indicating a Brown-out Reset occurred. When the Brown-out Reset is disabled, the state of the BOR bit is unpredictable. Bit 1 is POR (Power-on Reset Status bit). It is cleared on a Power-on Reset and unaffected otherwise. The user must set this bit following a Power-on Reset. TABLE 15-1: TIME-OUT IN VARIOUS SITUATIONS TABLE 15-2: STATUS BITS AND THEIR SIGNIFICANCE Oscillator Configuration Power-up Brown-out Reset Wake-up from Sleep PWRTE = 0 PWRTE = 1 PWRTE = 0 PWRTE = 1 XT, HS, LP TPWRT + 1024 • TOSC 1024 • TOSC TPWRT + 1024 • TOSC 1024 • TOSC 1024 • TOSC EXTRC, INTRC TPWRT 5-10 s(1) TPWRT 5-10 s(1) 5-10 s(1) T1OSC — ——— 5-10 s(1) Note 1: CPU start-up is always invoked on POR, BOR and wake-up from Sleep. The 5-10 s delay is based on a 1 MHz system clock. POR BOR TO PD 0x1 1 Power-on Reset 0x0 x Illegal, TO is set on POR 0xx 0 Illegal, PD is set on POR 101 1 Brown-out Reset 110 1 WDT Reset 110 0 WDT Wake-up 11u u MCLR Reset during Normal Operation 111 0 MCLR Reset during Sleep or Interrupt Wake-up from Sleep Legend: u = unchanged, x = unknown |
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