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PIC18F23K20 Datasheet(PDF) 39 Page - Microchip Technology |
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PIC18F23K20 Datasheet(HTML) 39 Page - Microchip Technology |
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39 / 42 page ![]() © 2009 Microchip Technology Inc. Advance Information DS41297F-page 39 PIC18F2XK20/4XK20 P12 THLD2 Input Data Hold Time from MCLR/VPP/RE3 ↑ 2— μs P13 TSET2VDD ↑ Setup Time to MCLR/VPP/RE3 ↑ 100 — ns P14 TVALID Data Out Valid from PGC ↑ 10 — ns P15 TSET3PGM ↑ Setup Time to MCLR/VPP/RE3 ↑ 2— μs P16 TDLY8 Delay between Last PGC ↓ and MCLR/VPP/RE3 ↓ 0— s P17 THLD3MCLR/VPP/RE3 ↓ to VDD ↓ — 100 ns P18 THLD4MCLR/VPP/RE3 ↓ to PGM ↓ 0— s P19 THIZ Delay from PGC ↑ to PGD High-Z 3 10 nS P20 TPPDP Hold time after VPP changes 5 — μs 6.0 AC/DC CHARACTERISTICS TIMING REQUIREMENTS FOR PROGRAM/ VERIFY TEST MODE (CONTINUED) Standard Operating Conditions Operating Temperature: 25 °C is recommended Param No. Sym. Characteristic Min. Max. Units Conditions Note 1: Do not allow excess time when transitioning MCLR between VIL and VIHH; this can cause spurious program executions to occur. The maximum transition time is: 1 TCY + TPWRT (if enabled) + 1024 TOSC (for LP, HS, HS/PLL and XT modes only) + 2 ms (for HS/PLL mode only) + 1.5 μs (for EC mode only) where TCY is the instruction cycle time, TPWRT is the Power-up Timer period and TOSC is the oscillator period. For specific values, refer to the Electrical Characteristics section of the device data sheet for the particular device. |
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