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PIC18LF2X Datasheet(PDF) 39 Page - Microchip Technology |
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PIC18LF2X Datasheet(HTML) 39 Page - Microchip Technology |
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39 / 44 page ![]() 2012 Microchip Technology Inc. DS41630B-page 39 PIC18(L)F2X/4XK50 6.0 AC/DC CHARACTERISTICS TIMING REQUIREMENTS FOR PROGRAM/ VERIFY TEST MODE Standard Operating Conditions Operating Temperature: 25 C is recommended Param No. Sym. Characteristic Min. Max. Units Conditions D110 VIHH High-Voltage Programming Voltage on MCLR/VPP/RE3 8 9 V D111 VDD Supply Voltage (VDDMIN, VDDMAX) PIC18LF 1.8 3.6 V PIC18F 2.3 5.5 V D111A VPEW Voltage during Write or Erase Operations PIC18LF 2.2V VDDMAX V Row Erase/Write PIC18F VDDMIN VDDMAX D111B VBULK Voltage during Bulk Erase Operations 2.7 VDDMAX V Bulk Erase operations D112 IPP Programming Current on MCLR/VPP/RE3 — 300 A D113 IDDP Supply Current During Programming —10 mA D031 VIL Input Low Voltage VSS 0.2 VDD V D041 VIH Input High Voltage 0.8 VDD VDD V D080 VOL Output Low Voltage —0.6 V IOL = 8.5 mA @ 3.0V D090 VOH Output High Voltage VDD – 0.7 — V IOH = 3.0 mA @ 3.0V D012 CIO Capacitive Loading on I/O pin (PGD) — 50 pF To meet AC specifications P1 TR MCLR/VPP/RE3 Rise Time to enter Program/Verify mode — 1.0 s (Note 1) P2 TPGC Serial Clock (PGC) Period 100 — ns VDD = 3.6V 1— sVDD = 1.8V P2A TPGCL Serial Clock (PGC) Low Time 40 — ns VDD = 3.6V 400 — ns VDD = 1.8V P2B TPGCH Serial Clock (PGC) High Time 40 — ns VDD = 3.6V 400 — ns VDD = 1.8V P3 TSET1 Input Data Setup Time to Serial Clock 15 — ns P4 THLD1 Input Data Hold Time from PGC 15 — ns P5 TDLY1 Delay between 4-bit Command and Command Operand 40 — ns P5A TDLY1A Delay between 4-bit Command Operand and next 4-bit Command 40 — ns P6 TDLY2 Delay between Last PGC of Command Byte to First PGC of Read of Data Word 20 — ns P9 TDLY5 PGC High Time (minimum programming time) 1 — ms Externally Timed P9A TDLY5A PGC High Time 5 ms Configuration Word programming time P10 TDLY6 PGC Low Time after Programming (high-voltage discharge time) 200 — s P11 TDLY7 Delay to allow Self-Timed Bulk Erase to occur PIC18(L)FX5K50 PIC18(L)FX6K50 15 — ms PIC18(L)F24K50 12 — ms P11A TDRWT Data Write Polling Time 4 — ms Note 1: Do not allow excess time when transitioning MCLR between VIL and VIHH; this can cause spurious program executions to occur. The maximum transition time is: 1 TCY + TPWRT (if enabled) + 1024 TOSC (for LP, HS, HS/PLL and XT modes only) + 2 ms (for HS/PLL mode only) + 1.5 s (for EC mode only) where TCY is the instruction cycle time, TPWRT is the Power-up Timer period and TOSC is the oscillator period. For specific values, refer to the Electrical Characteristics section of the device data sheet for the particular device. |
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